MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 108

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Operations
Initialization
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
10. Issue a ZQCL command to calibrate R
11. When
1. Apply power. RESET# is recommended to be below 0.2 × V
2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled
3. CKE must be LOW 10ns prior to RESET# transitioning HIGH.
4. After RESET# transitions HIGH, wait 500µs (minus one clock) with CKE LOW.
5. After this CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP
6. After CKE is registered HIGH and after
7. Issue an MRS command to MR3 with the applicable settings.
8. Issue an MRS command to MR1 with the applicable settings, including enabling the
9. Issue an MRS command to MR0 with the applicable settings, including a DLL RESET
The following sequence is required for power up and initialization, as shown in Figure 48
on page 109:
During power up, either of the following conditions may exist and must be met:
• Condition A:
• Condition B:
ensure the outputs remain disabled (High-Z) and ODT off (R
other inputs, including ODT, may be undefined.
– V
– Both V
– V
– V
– V
– V
– No slope reversals are allowed in the power supply ramp for this condition.
(High-Z). After the power is stable, RESET# must be LOW for at least 200µs to begin
the initialization process. ODT will remain in the High-Z state while RESET# is LOW
and until CKE is registered HIGH.
or DES commands may be issued. The clock must be present and valid for at least
10ns (and a minimum of five clocks) and ODT must be driven LOW at least
CKE being registered HIGH. When CKE is registered HIGH, it must be continuously
registered HIGH until the full initialization process is complete.
be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings
(provide LOW to BA2 and BA0 and HIGH to BA1).
DLL and configuring ODT.
command.
perature (PVT). Prior to normal operation,
mal operation.
with a maximum delta voltage between them of ΔV
power supply signal is allowed. The voltage levels on all balls other than V
V
must be greater than or equal to V
t
to the device; however,
latchup.
V
REF
DD
DD
TT
DD
DD
DDPR
t
is limited to 0.95V when the power ramp is complete and is not applied directly
Q, V
Q may be applied before or at the same time as V
DQ tracks V
DLLK and
and V
may be applied before or at the same time as V
DD
= 200ms.
SS
t
DLLK (512) cycles of clock input are required to lock the DLL.
and V
, V
DD
SS
Q are driven from a single-power converter output and are ramped
Q must be less than or equal to V
t
ZQ
DD
DD
Q power supplies ramp to V
INIT
× 0.5, V
have been satisfied, the DDR3 SDRAM will be ready for nor-
t
108
VTD should be greater than or equal to zero to avoid device
REF
CA tracks V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SS
TT
Q and V
t
XPR has been satisfied, MRS commands may
and R
t
ZQ
DD
ON
2Gb: x4, x8, x16 DDR3 SDRAM
INIT
SS
× 0.5.
on the other side.
DD
values for the process voltage tem-
DD
must be satisfied.
(MIN) and V
Q and V
≤
DD
TT
300mV. Slope reversal of any
Q.
, V
DD
©2006 Micron Technology, Inc. All rights reserved.
REF
TT
Q during power ramp to
DD
is also High-Z). All
DQ, and V
on one side, and
DD
Q (MIN) within
Operations
REF
t
IS prior to
DD
CA.
,