MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 115

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Mode Register 1 (MR1)
Figure 53: Mode Register 1 (MR1) Definition
DLL Enable/DLL Disable
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
M15
0
0
1
1
M14
0
1
0
1
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
Notes:
Mode Register
The mode register 1 (MR1) controls additional functions and features not available in
the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration
only), DLL ENABLE/DLL DISABLE, R
CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are
controlled via the bits shown in Figure 53. The MR1 register is programmed via the MRS
command and retains the stored information until it is reprogrammed, until RESET#
goes LOW, or until the device loses power. Reprogramming the MR1 register will not
alter the contents of the memory array, provided it is performed correctly.
The MR1 register must be loaded when all banks are idle and no bursts are in progress.
The controller must satisfy the specified timing parameters
initiating a subsequent operation.
1. MR1[16, 13, 10, 8] are reserved for future use and must be programmed to “0.”
2. During write leveling, if MR1[7] and MR1[12] are “1” then all R
3. During write leveling, if MR1[7] is a “1,” but MR1[12] is a “0,” then only R
The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE
command, as shown in Figure 53. The DLL must be enabled for normal operation. DLL
enable is required during power-up initialization and upon returning to normal opera-
tion after having disabled the DLL for the purpose of debugging or evaluation. Enabling
the DLL should always be followed by resetting the DLL using the appropriate LOAD
MODE command.
If the DLL is enabled prior to entering self refresh mode, the DLL is automatically
disabled when entering SELF REFRESH operation and is automatically reenabled and
reset upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self
refresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation
until it is reenabled and reset.
for use.
ues are available for use.
M9
0
0
0
0
1
1
1
1
0 1
M6
BA2
16
0
0
1
1
0
0
1
1
M12
0
1
M2
0
1
0
1
0
1
0
1
0
BA1
15
Disabled
Enabled
RZQ/2 (120Ω [NOM])
RZQ/12 (20Ω [NOM])
RZQ/4 (60Ω [NOM])
RZQ/6 (40Ω [NOM])
RZQ/8 (30Ω [NOM])
Q Off
14
1
R
BA0
R
TT
TT
Non-Writes
_
0 1
_
Reserved
Reserved
NOM
13
NOM
A13
Q Off
disabled
M11
12
(ODT)
A12 A11
0
1
TDQS
11
Disabled
Enabled
2
TDQS
0 1
10
A10
RZQ/2 (120Ω [NOM])
RZQ/4 (60Ω [NOM])
RZQ/6 (40Ω [NOM])
115
R
R
R
TT
TT
TT
9
A9
_
_
Reserved
Reserved
NOM
NOM
Writes
0 1
n/a
n/a
8
A8
disabled
(ODT)
WL
7
A7 A6 A5 A4 A3
TT
R
3
TT
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
_
ODS
NOM
5
M4
M7
0
0
1
1
0
1
4
M3
AL
Write Levelization
0
1
0
1
Disable (normal)
value (ODT), WRITE LEVELING, POSTED
3
Additive Latency (AL)
Enable
R
Disabled (AL = 0)
TT
2
2Gb: x4, x8, x16 DDR3 SDRAM
A2 A1 A0
AL = CL - 1
AL = CL - 2
ODS DLL
Reserved
1
0
M5
Address bus
Mode register 1 (MR1)
0
0
1
1
t
MRD and
M0
M1
0
1
0
1
0
1
TT
©2006 Micron Technology, Inc. All rights reserved.
_
Output Drive Strength
NOM
RZQ/6 (40Ω [NOM])
RZQ/7 (34Ω [NOM])
Enable (normal)
DLL Enable
Disable
Reserved
Reserved
values are available
t
MOD before
TT
_
Operations
NOM
write val-