MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 129

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Figure 63: ZQ Calibration Timing (ZQCL and ZQCS)
ACTIVATE
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
Command
Address
ODT
CK#
A10
CKE
DQ
CK
ZQCL
1
2
3
T0
Notes:
NOP
DDR3 SDRAM need a longer time to calibrate R
and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3
SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL)
and ZQ CALIBRATION SHORT (ZQCS). An example of ZQ calibration timing is shown in
Figure 63.
All banks must be precharged and
can be issued to the DRAM. No other activities (other than another ZQCL or ZQCS
command may be issued to another DRAM) can be performed on the DRAM channel by
the controller for the duration of
channel helps accurately calibrate R
the DRAM should disable the ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must not
allow overlap of
T1
1. CKE must be continuously registered HIGH during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
3. All devices connected to the DQ bus should be High-Z during calibration.
Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE
command, which selects both the bank and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may be
issued to that row, subject to the
programmed correctly, a READ or WRITE command may be issued prior to
In this operation, the DRAM enables a READ or WRITE command to be issued after the
ACTIVATE command for that bank, but prior to
(ACTIVATE-to-READ/WRITE) + AL ≥
(AL)” on page 117).
t ZQ
High-Z
NOP
Ta0
INIT
or t ZQ
OPER
NOP
t
Ta1
ZQ
t
INIT
RCD (MIN) should be divided by the clock period and rounded up to
,
Valid
Valid
Valid
Valid
Valid
t
Ta2
ZQ
OPER
129
Activities
Valid
Valid
Valid
Valid
t
, or
Valid
t
Ta3
RCD specification. However, if the additive latency is
ZQ
t
RP must be met before ZQCL or ZQCS commands
ON
INIT
t
t
ZQ
RCD (MIN) (see “POSTED CAS ADDITIVE Latency
Micron Technology, Inc., reserves the right to change products or specifications without notice.
and ODT. After DRAM calibration is achieved,
CS
or
ZQCS
Tb0
between ranks.
1
2
3
t
ZQ
OPER
ON
t
RCD (MIN) with the requirement that
2Gb: x4, x8, x16 DDR3 SDRAM
NOP
Tb1
and ODT at power-up initialization
. The quiet time on the DRAM
Indicates a Break in
Time Scale
High-Z
NOP
t ZQCS
Tc0
©2006 Micron Technology, Inc. All rights reserved.
NOP
Tc1
Don’t Care
Operations
Valid
Valid
Valid
Valid
Valid
t
Tc2
RCD (MIN).
Activ-
ities