MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 132

no-image

MT41J256M8HX-15E:D

Manufacturer Part Number
MT41J256M8HX-15E:D
Description
MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Series
-r
Datasheets

Specifications of MT41J256M8HX-15E:D

Organization
256Mx8
Address Bus
18b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
165mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (256M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-TFBGA
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
SAMSUNG
Quantity:
1 001
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
MICRON
Quantity:
11 200
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
MICRON21
Quantity:
1 684
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
MICRON21
Quantity:
16 491
Company:
Part Number:
MT41J256M8HX-15E:D
Quantity:
5 845
Part Number:
MT41J256M8HX-15E:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
Data from any READ burst must be completed before a subsequent WRITE burst is
allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in
Figure 70 on page 134 (BC4 is shown in Figure 71 on page 135). To ensure the read data is
completed before the write data is on the bus, the minimum READ-to-WRITE timing is
RL +
A READ burst may be followed by a PRECHARGE command to the same bank provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command
spacing to the same bank is four clocks and must also satisfy a minimum analog time
from the READ command. This time is called
AL cycles later than the READ command. Examples for BL8 are shown in Figure 72 on
page 135 and BC4 in Figure 73 on page 136. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until
PRECHARGE command followed by another PRECHARGE command to the same bank
is allowed. However, the precharge period will be determined by the last PRECHARGE
command issued to the bank.
If A10 is HIGH when a READ command is issued, the READ with auto precharge function
is engaged. The DRAM starts an auto precharge operation on the rising edge which is AL
+
Figure 75 on page 136). If
auto precharge operation will be delayed until
not satisfied at the edge, the starting point of the auto precharge operation will be
delayed until
t
rising clock edge after this event). The time from READ with auto precharge to the next
ACTIVATE command to the same bank is AL + (
up to the next integer. In any event, internal precharge does not start earlier than four
clocks after the last 8n-bit prefetch.
RTP,
t
RTP cycles after the READ command. DRAM support a
t
t
CCD - WL + 2
RP starts at the point at which the internal precharge happens (not at the next
t
RTP (MIN) is satisfied. In case the internal precharge is pushed out by
t
CK.
t
RAS (MIN) is not satisfied at the edge, the starting point of the
132
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RTP (READ-to-PRECHARGE).
t
t
RAS (MIN) is satisfied. If
RTP +
2Gb: x4, x8, x16 DDR3 SDRAM
t
RP)*, where “*” means rounded
t
RAS lockout feature (see
©2006 Micron Technology, Inc. All rights reserved.
t
RP is met. The
t
RTP (MIN) is
Operations
t
RTP starts

Related parts for MT41J256M8HX-15E:D