MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 163

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Dynamic ODT
Functional Description
Table 80:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D5.fm - Rev G 2/09 EN
Symbol
ODTL
ODTL
ODTL
t
ADC
CNW
CWN
CWN
4
8
Dynamic ODT Specific Parameters
Change from R
Change from R
Change from R
R
R
R
TT
Description
TT
TT
change skew
_
_
R
NOM
NOM
TT
In certain application cases, and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the DDR3 SDRAM can be changed without
issuing an MRS command, essentially changing the ODT termination on the fly. With
dynamic ODT (R
dynamic ODT (R
to nominal ODT (R
supported by the dynamic ODT feature, as described below:
The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to “1.” Dynamic
ODT is not supported during DLL disable mode so R
dynamic ODT function is described, as follows:
• Two R
• During DRAM operation without READ or WRITE commands, the termination is
• When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered,
ODT is constrained during writes and when dynamic ODT is enabled (see Table 80).
ODT timings listed in Table 79 on page 162 also apply to dynamic ODT mode.
_
WR
– The value for R
– The value for R
controlled as follows:
– Nominal termination strength R
– Termination on/off timing is controlled via the ODT ball and latencies ODTL on
and if dynamic ODT is enabled, the ODT termination is controlled as follows:
– A latency of ODTL
– A latency of ODTL
– On/off termination timing is controlled via the ODT ball and determined by ODTL
– During the
(BC4)
(BL8)
TT
TT
TT
and ODTL off
switches to R
OTF) after the WRITE command: termination strength R
R
on, ODTL off, ODTH4, and ODTH8
_
_
_
TT
NOM
WR
WR
TT
_
NOM
to
to
to
values are available—R
ODTL
TT
t
Write registration
Write registration
Write registration
TT
ADC transition window, the value of R
TT
_
_
TT
WR
WR
Begins at
TT
TT
CNW
_
_
WR
NOM
_
_
) when beginning a WRITE burst and subsequently switches back
) enabled, the DRAM switches from nominal ODT (R
CNW
CWN
NOM
WR
completed
) at the completion of the WRITE burst. This requirement is
is preselected via MR2[10, 9]
8 (for BL8, fixed or OTF) or ODTL
after the WRITE command: termination strength R
is preselected via MR1[9, 6, 2]
163
TT
R
R
_
R
TT
TT
TT
NOM
TT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
R
_
switched from R
switched from R
R
TT
NOM
transition complete
TT
_
Defined to
and R
to R
to R
switched from
NOM
is used
TT
TT
to R
TT
_
_
2Gb: x4, x8, x16 DDR3 SDRAM
NOM
NOM
_
TT
WR
TT
_
WR
On-Die Termination (ODT)
_
TT
TT
:
TT
WR
_
_
WR
WR
is undefined
must be disabled. The
CWN
TT
Definition for All
DDR3 Speed Bins Units
©2006 Micron Technology, Inc. All rights reserved.
4
6
_
0.5
t
t
WR
CK + ODTL off
CK + ODTL off
4 (for BC4, fixed or
t
CK ±0.2
WL - 2
switches back to
t
CK
TT
_
NOM
TT
_
NOM
tCK
t
t
t
) to
CK
CK
CK