MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 77

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D3.fm - Rev G 2/09 EN
17. The cumulative jitter error (
18.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth)
20. The setup and hold times are listed converting the base specification values (to which
21. When the device is operated with input clock jitter, this parameter needs to be der-
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output
24. The maximum preamble is bound by
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its
26. The
27. The maximum postamble is bound by
28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT
29.
30. These parameters are measured from a command/address signal transition edge to
31. For these parameters, the DDR3 SDRAM device supports
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for
50, is the amount of clock time allowed to accumulate consecutively away from the
average clock over n number of clock cycles.
t
2 V/ns differential DQS, DQS# slew rate.
transition edge to its respective data strobe signal (DQS, DQS#) crossing.
derating tables apply) to V
rate of 1 V/ns, are for reference only.
ated by the actual
(output deratings are relative to the SDRAM input clock).
parameters must be derated by the actual jitter error when input clock jitter is pres-
ent, even when within specification. This results in each parameter becoming larger.
The following parameters are required to be derated by subtracting
t
parameters are required to be derated by subtracting
t
parameter
derated by subtracting
respective clock signal (CK, CK#) crossing. The specification values are not affected by
the amount of clock jitter applied, as these are relative to the clock signal crossing.
These parameters should be met whether clock jitter is present.
commands. In addition, after any change of latency
t
address slew rate and 2 V/ns CK, CK# differential slew rate.
its respective clock (CK, CK#) signal crossing. The specification values are not affected
by the amount of clock jitter applied as the setup and hold times are relative to the
clock signal crossing that latches the command/address. These parameters should be
met whether clock jitter is present.
RU(
isfied. For example, the device will support
clock jitter specifications are met. This means for DDR3-800 6-6-6, of which
t
clock jitter specifications are met. That is, the PRECHARGE command at T0 and the
ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to
input clock jitter.
internal PRECHARGE command until
DS (base) and
DQSCK (MIN),
DQSCK (MAX),
IS (base) and
RP = 15ns, the device will support
t
t
PARAM [ns]/
DQSCK
t
RPRE (MIN) is derated by subtracting
DLL
t
IH (base) values are for a single-ended 1 V/ns control/command/
t
DH (base) values are for a single-ended 1 V/ns DQ slew rate and
t
t
_
LZ (DQS) MIN,
HZ (MAX),
t
DIS
CK[AVG] [ns]), assuming all input clock jitter specifications are sat-
t
JIT
parameter begins CL + AL - 1 cycles after the READ command.
PER
t
JIT
(larger of
REF
PER
77
t
t
ERRn
LZ (DQS) MAX,
when the slew rate is 1 V/ns. These values, with a slew
(MIN).
t
LZ (DQ) MIN, and
PER
t
t
nRP = RU(
JIT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
), where n is the number of clocks between 2 and
t
LZDQS (MAX).
t
t
PER
RAS (MIN) has been satisfied.
HZDQS (MAX).
(MIN) or
t
nRP (nCK) = RU(
t
LZ (DQ) MAX, and
t
RP/
2Gb: x4, x8, x16 DDR3 SDRAM
t
JIT
t
CK[AVG]) = 6 as long as the input
t
t
JIT
AON (MIN). The following
t
PER
XPDLL, timing must be met.
t
ERR
PER
(MAX), while
t
10PER
nPARAM (nCK) =
(MAX) of the input clock
©2006 Micron Technology, Inc. All rights reserved.
t
RP/
Speed Bin Tables
(MIN):
t
t
AON (MAX). The
CK[AVG]) if all input
t
ERR
t
RPRE (MAX) is
10PER
(MAX):
t
WR.