MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 95

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

NO OPERATION (NOP)
ZQ CALIBRATION
ZQ CALIBRATION LONG (ZQCL)
ZQ CALIBRATION SHORT (ZQCS)
ACTIVATE
READ
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
The NOP command (CS# LOW) prevents unwanted commands from being registered
during idle or wait states. Operations already in progress are not affected.
The ZQCL command is used to perform the initial calibration during a power-up initial-
ization and reset sequence (see Figure 48 on page 109). This command may be issued at
any time by the controller depending on the system environment. The ZQCL command
triggers the calibration engine inside the DRAM. After calibration is achieved, the cali-
brated values are transferred from the calibration engine to the DRAM I/O, which are
reflected as updated R
The DRAM is allowed a timing window defined by either
the full calibration and transfer of values. When ZQCL is issued during the initialization
sequence, the timing parameter
complete, subsequent ZQCL commands require the timing parameter
satisfied.
The ZQCS command is used to perform periodic calibrations to account for small
voltage and temperature variations. The shorter timing window is provided to perform
the reduced calibration and transfer of values as defined by timing parameter
ZQCS command can effectively correct a minimum of 0.5% R
error within 64 clock cycles, assuming the maximum sensitivities specified in Table 43
on page 59 and Table 44 on page 60.
The ACTIVATE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA[2:0] inputs selects the bank, and the address
provided on inputs A[n:0] selects the row. This row remains open (or active) for accesses
until a PRECHARGE command is issued to that bank.
A PRECHARGE command must be issued before opening a different row in the same
bank.
The READ command is used to initiate a burst read access to an active row. The address
provided on inputs A[2:0] selects the starting column address depending on the burst
length and burst type selected (see Table 71 on page 113 for additional information). The
value on input A10 determines whether or not auto precharge is used. If auto precharge
is selected, the row being accessed will be precharged at the end of the READ burst. If
auto precharge is not selected, the row will remain open for subsequent accesses. The
value on input A12 (if enabled in the mode register) when the READ command is issued
determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the
READ burst may not be interrupted. A summary of READ commands is shown in
Table 67 on page 96.
ON
and ODT values.
95
t
ZQ
INIT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
must be satisfied. When initialization is
2Gb: x4, x8, x16 DDR3 SDRAM
t
ZQ
INIT
ON
©2006 Micron Technology, Inc. All rights reserved.
and R
or
t
ZQ
TT
t
OPER
ZQ
impedance
Commands
OPER
to perform
t
ZQCS. A
to be