MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 96

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Table 67:
WRITE
Table 68:
PRECHARGE
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
Function
Function
READ
READ
with auto
precharge
WRITE
WRITE with
auto
precharge
BL8MRS, BC4MRS
BL8MRS, BC4MRS
READ Command Summary
WRITE Command Summary
BL8MRS, BC4MRS
BL8MRS, BC4MRS
BC4OTF
BC4OTF
BL8OTF
BL8OTF
BC4OTF
BC4OTF
BL8OTF
BL8OTF
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or
not auto precharge is used. The value on input A12 (if enabled in the MR) when the
WRITE command is issued determines whether BC4 (chop) or BL8 is used. The WRITE
command summary is shown in Table 68.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW, the
corresponding data will be written to memory. If the DM signal is registered HIGH, the
corresponding data inputs will be ignored and a WRITE will not be executed to that
byte/column location.
The PRECHARGE command is used to deactivate the open row in a particular bank or in
all banks. The bank(s) are available for a subsequent row access a specified time (
after the PRECHARGE command is issued, except in the case of concurrent auto
precharge. A READ or WRITE command to a different bank is allowed during concurrent
auto precharge as long as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Input A10 determines whether one or all
banks are precharged. In the case where only one bank is precharged, inputs BA[2:0]
select the bank; otherwise, BA[2:0] are treated as “Don’t Care.” After a bank is
precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command is treated as a NOP if
Symbol
RDAPS4
RDAPS8
RDAP
RDS4
RDS8
RD
WRAPS4
WRAPS8
Symbol
WRAP
WRS4
WRS8
WR
Previous
Cycle
Cycle
Prev
CKE
H
H
H
H
H
H
CKE
H
H
H
H
H
H
Cycle
Next
Cycle
Next
CS# RAS# CAS# WE#
CS# RAS# CAS# WE#
96
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
Micron Technology, Inc., reserves the right to change products or specifications without notice.
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
2Gb: x4, x8, x16 DDR3 SDRAM
H
H
H
H
H
H
[3:0]
[3:0]
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
An
An
©2006 Micron Technology, Inc. All rights reserved.
A12
A12
V
H
V
H
H
V
H
V
L
L
L
L
Commands
A10
A10
H
H
H
H
H
H
L
L
L
L
L
L
t
A[11,
A[11,
RP)
9:0]
9:0]
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA