RC28F640J3F75A NUMONYX, RC28F640J3F75A Datasheet
RC28F640J3F75A
Specifications of RC28F640J3F75A
Available stocks
Related parts for RC28F640J3F75A
RC28F640J3F75A Summary of contents
Page 1
... Individual block locking — Block erase/program lockout during power transitions — Password Access feature — One-Time Programmable Register: 64 OTP bits, programmed with unique information by Numonyx 64 OTP bits, available for customer programming Software — Program and erase suspend support ® — Numonyx Flash Data Integrator (FDI) — ...
Page 2
... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the Numonyx website at http://www.numonyx.com. ...
Page 3
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Contents 1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Acronyms........................................................................................................... 7 1.3 Conventions ....................................................................................................... 7 2.0 Functional Overview .................................................................................................. 9 2.1 Block Diagram .................................................................................................. 11 2.2 Memory Map..................................................................................................... 12 3.0 Package Information ............................................................................................... 13 3.1 56-Lead TSOP Package for 32-, 64-, 128-Mbit ....................................................... 13 3.2 64-Ball Easy BGA Package for 32-, 64-, 128-Mbit .................................................. 14 4 ...
Page 4
... Block Status Register .........................................................................................60 13.4 CFI Query Identification String ............................................................................60 13.5 System Interface Information..............................................................................61 13.6 Device Geometry Definition .................................................................................61 13.7 Primary-Vendor Specific Extended Query Table ......................................................62 A Additional Information.............................................................................................65 B Ordering Information...............................................................................................66 Datasheet 4 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) March 2010 208032-02 ...
Page 5
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Revision History Date Revision Description May 2009 01 Initial release Add Blank Check function and command. Add Blank Check specification tBC/MB, update Clear Block Lock-Bits Max Time and Program time in Update I Order information with device features digit ...
Page 6
... This document contains information pertaining to the Numonyx Memory (J3 65 nm) Single Bit per Cell (SBC) device features, operation, and specifications. Unless otherwise indicated throughout the rest of this document, the Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) device is referred SBC. ...
Page 7
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 1.2 Acronyms SBC Single Bit per Cell FDI Flash Data Integrator CFI Common Flash Interface SCS Scalable Command Set CUI Command User Interface OTP One Time Programmable PLR Protection Lock Register ...
Page 8
... A[21:1], SR[4,1] and D[15:0]). 00FFh Denotes 16-bit hexadecimal numbers 00FF 00FFh Denotes 32-bit hexadecimal numbers DQ[15:0] Data I/O signals Datasheet 8 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) March 2010 208032-02 ...
Page 9
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 2.0 Functional Overview The SBC family contains high-density memory organized in any of the following configurations: • 16-MB or 8-MW (128-Mbit), organized as one-hundred-twenty-eight 128-KB erase blocks. • 8-MB or 4-MW (64-Mbit), organized as sixty-four 128-KB erase blocks. ...
Page 10
... PHWL V , the WSM is reset and the Status Register is cleared. IL Datasheet 10 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Table 17, “Chip Enable Truth Table for 32-, 64-, 128- and RP from RP#-high until writes to the CUI are recognized. With RP# at 30) reduces shows a device , the standby mode is enabled ...
Page 11
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 2.1 Block Diagram Figure 1: Memory Block Diagram for 32-, 64-, 128-Mbit March 2010 208032-02 Datasheet 11 ...
Page 12
... 128 KB Block 127 128 KB Block 128 KB Block 128 KB Block 128 KB Block - Byte-Wide ( Mode Datasheet 12 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) A [23:1]:128 Mbit A [22:1]: 64Mbit A [21:1]: 32Mbit Word-Wide (x16) Mode - 64 KW Block 127 - 64 KW Block Block ...
Page 13
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 3.0 Package Information 3.1 56-Lead TSOP Package for 32-, 64-, 128-Mbit Figure 3: 56-Lead TSOP Package Mechanical Z Pin 1 See Detail A Detail A Notes: 1. One dimple on package denotes Pin two dimples, then the larger dimple denotes Pin 1. ...
Page 14
... Table 2: Easy BGA Package Dimensions Table (Sheet Parameter Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Datasheet 14 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Millimeters Min Nom N — 56 0° 3° θ ...
Page 15
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Table 2: Easy BGA Package Dimensions Table (Sheet Parameter Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E March 2010 208032-02 Millimeters ...
Page 16
... A22 is valid for 64-Mbit density and above. On 32-Mbit no-connect (NC). 3. A23 is valid for 128-Mbit density. On 32- and 64-Mbit no-connect (NC). 4. A24 connect (NC) on 128-, 64-, 32- Mbit, reserved for 256-Mbit. Datasheet 16 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC (2) ...
Page 17
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 4.2 56-Lead TSOP Package Pinout for 32-, 64-,128-Mbit Figure 6: 56-Lead TSOP Package Pinout (32/64/128 Mbit) ( CE1 (1) VCC Numonyx CE0 14 VPEN 15 RP VSS Notes internal connection for pin 9; it may be driven or floated. For legacy designs, the pin can be tied ...
Page 18
... VSS Supply GROUND: Ground reference for device logic voltages. Connect to system ground. NC — No Connect: Lead is not internally connected; it may be driven or floated. Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device RFU — functionality and enhancement. Datasheet 18 ® ...
Page 19
... These are stress ratings only. NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design. Table 4: Absolute Maximum Ratings ...
Page 20
... See Waveform for Reset Operation” on page 28 timings. Datasheet 20 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 1st (1) 1st Sequencing not (1) ...
Page 21
... CC I Suspend Current CCES Notes: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Numonyx or your local sales office for information about typical specifications. 2. Includes STS. 3. CMOS inputs are either V ± 0 ...
Page 22
... Capacitance Symbol OUT Notes: 1. Sampled, not 100% tested -40 °C to +85 ° Datasheet 22 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 2.7 - 3.6 V 2.7 - 3.6 V Min Max –0.5 0.8 2 0.5 CCQ — 0.4 — 0.2 0.85 × V — CCQ V 0 ...
Page 23
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 7.0 AC Characteristics Timing symbols used in the timing diagrams within this document conform to the following convention. Figure 7: Timing Signal Naming Convention Source Signal Source State Table 10: Timing Signal Name Decoder Signal ...
Page 24
... See Equivalent Testing Load Circuit” on page 29 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 (t Datasheet 24 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) (3) = 2.7 V–3.6 V and V CC Density All 32 Mbit 64 Mbit 128 Mbit ...
Page 25
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Figure 8: Single-Word Asynchronous Read Waveform Address [A] CEx [ [G] WE# [W] DQ[15:0] [Q] BYTE# [F] RP Notes low is defined as the combination of pins CE0, CE1, and CE2 that enable the device combination of pins CE0, CE1, and CE2 that disable the device (see , 64-, 128-Mb” ...
Page 26
... AVQV 9. STS timings are based on STS configured in its RY/BY# default mode. 10. V should be held at V PEN PENH = 0). Datasheet 26 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Parameter Density 32 Mbit ) Going Low 64 Mbit X 128 Mbit ) Going Low X ) Going High ...
Page 27
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Figure 10: Asynchronous Write Waveform Address [A] CEx (WE#) [E (W)] WE# (CEx) [W (E)] OE# [G] DATA [D/Q ] STS [R] RP# [P] VPEN [V] Figure 11: Asynchronous Write to Read Waveform Address [A] CEx [E] WE# [ [G] DATA [D/Q] W1 RP# [P] VPEN [V ] March 2010 ...
Page 28
... RP# (P) Vcc Note: STS is shown in its default mode (RY/BY#). Datasheet 28 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Parameter Single word Aligned 16 Words BP Time (32Byte) Aligned 256 Words BP Time (512Byte) Array Block = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to ...
Page 29
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Table 14: Reset Specifications # Symbol RP# Pulse Low Time (If RP# is tied PLPH specification is not applicable) RP# High to Reset during Block Erase, Program, or Lock-Bit P2 t PHRH Configuration P3 t Vcc Power Valid to RP# de-assertion (high) ...
Page 30
... Array writes are either program or erase operations. Table 17: Chip Enable Truth Table for 32-, 64-, 128-Mb CE2 Note: For single-chip applications, CE2 and CE1 can be connected to VSS. Datasheet 30 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) (1) (2) (2) CE OE# WE Enabled Enabled ...
Page 31
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 8.1 Bus Reads Reading from flash memory outputs stored information to the processor or chipset, and does not change any contents. Reading can be performed an unlimited number of times. Besides array data, other types of data such as device information and device status is available from the flash ...
Page 32
... WE CE0, CE1, and CE2 that enable the device. CE pins CE0, CE1, and CE2 that disable the device. See microprocessor write timings are used. Datasheet 32 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Reserved ECR ECR ECR ECR ...
Page 33
... Flash commands fall into two categories: Basic Commands and Extended Commands. Basic commands are recognized by all Numonyx Flash devices, and are used to perform common flash operations such as selecting the read mode, programming the array, or erasing blocks. ...
Page 34
... Program Suspend Status 1 Block-Locked Error 0 Reserved Datasheet 34 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Chapter 8.0, “Bus Interface”). A complete list of available Section 11.0, “Device Command Codes” on page or the device must be disabled before further reads to IH voltage. ...
Page 35
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 9.1.1 Clearing the Status Register The Status Register (SR) contain Status and error bits which are set by the device. SR status bits are cleared by the device, however SR error bits are cleared by issuing the ...
Page 36
... This is followed by writing the desired data at the desired array address. The read mode of the device is automatically changed to Read Status Register mode, which remains in effect until another read-mode command is issued. Datasheet 36 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) March 2010 208032-02 ...
Page 37
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) During programming, STS and the Status Register indicate a busy status (SR.7 = 0). Upon completion, STS and the Status Register indicate a ready status (SR.7 = 1). The Status Register should be checked for any errors (SR.4), then cleared. ...
Page 38
... Information, CFI Query, and Erase Suspend. After the block-erase operation has completed, any valid command can be issued. Datasheet 38 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Section 9.3, “Programming Operations”). Erasing is performed Table 23 shows the two-cycle Block Erase command sequence. ...
Page 39
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Note: Issuing the Read Array command to the device while it is actively erasing causes subsequent reads from the device to output invalid data. Valid array data is output only after the block-erase operation has finished. ...
Page 40
... A block-erase under program-suspend is not allowed. However, word-program under erase-suspend is allowed, and can be suspended. This results in a simultaneous erase- suspend/ program-suspend condition, indicated by SR[7,6, Datasheet 40 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Setup Write Cycle Address Bus Data Bus Device Address ...
Page 41
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) To resume a suspended program or erase operation, issue the Resume command to any device address. The read mode of the device is automatically changed to Read Status Register. The operation continues where it left off, STS (in RY/BY# mode) goes low, and the respective Status Register bits are cleared ...
Page 42
... SBC has the capability of Flexible Block Locking (locked blocks remain locked upon reset or power cycle): All blocks within the device are in unlocked state when ship from Numonyx. Blocks can be locked individually by issuing the Set Block Lock Bit command sequence to any address within a block. Once locked, blocks remain locked when power is removed, or when the device is reset ...
Page 43
... CPU or ASIC, hence preventing device substitution. The 128-bits of the PR are divided into two 64-bit segments: • One segment is programmed at the Numonyx factory with a unique unalterable 64- bit number. • The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent further programming ...
Page 44
... The user-programmable segment of the PR is lockable by programming Bit 1 of the Protection Lock Register (PLR Bit 0 of this location is programmed the Numonyx factory to protect the unique device number. Bit 1 is set using the Protection Program command to program “0xFFFD” to the PLR. After these bits have been programmed, no further changes can be made to the values stored in the Protection Register ...
Page 45
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Table 31: Word-Wide Protection Register Addressing Word Use LOCK Both 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User Note: All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.) ...
Page 46
... Status Register. By holding VPP or VPEN low, absolute write protection of all blocks in the array can be achieved. Datasheet 46 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) March 2010 208032-02 ...
Page 47
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 10.0 ID Codes Table 33: Read Identifier Codes Code Device Code March 2010 208032-02 Address 32-Mbit 00001h 64-Mbit 00001h 128-Mbit 00001h Data 0016h 0017h 0018h Datasheet 47 ...
Page 48
... Program/Erase Suspend Program/Erase Resume Set Block Lock Bit Clear Block Lock Bits Blank Check Datasheet 48 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Section 8.4, “Device Commands” Setup Write Cycle Address Bus Data Bus Register Data 0060h ...
Page 49
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 12.0 Flow Charts Figure 16: Write to Buffer Flowchart Start Setup - Write 0xE8 - Block Address Check Buffer Status - Perform Read Operation - Read Ready Status on signal SR.7 (Note 1) SR Yes Word Count - Address = block address ...
Page 50
... Data = 0x70 - Read Status Register SR[7:0] - Set/Reset by WSM - Set by WSM - Reset by user - See Clear Status Register Command Datasheet 50 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Start Data Cycle No SR7 = '1' Yes Y es Erase Suspend SR6 = '1' See Suspend/Resume Flowchart No ...
Page 51
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Figure 18: Byte/Word Program Flowchart Start Write 40H, Address Write Data and Address Read Status Register 0 SR Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data ...
Page 52
... Write B0H Read Status Register SR SR Write FFH Read Data Array Done Reading Yes Write D0H Programming Resumed Datasheet 52 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Bus Operation Write Read Standby Standby 0 Write Read 0 Programming Completed Write No ...
Page 53
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Figure 20: Block Erase Flowchart Start Issue Single Block Erase Command 20H, Block Address Write Confirm D0H Block Address Read Status Register 0 SR Full Status Check if Desired Erase Flash Block(s) Complete ...
Page 54
... SR Read Read or Program? Read Array No Data Done? Yes Write D0H Block Erase Resumed Datasheet 54 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Bus Operation Write Read Standby Standby 0 Write 0 Block Erase Completed Program Program Loop Write FFH ...
Page 55
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Figure 22: Set Block Lock-Bit Flowchart Start Write 60H, Block Address Write 01H, Block Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
Page 56
... SR SR.4 SR Clear Block Lock-Bits Successful Datasheet 56 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Bus Operation Write Write Lock-Bits Confirm Read Standby Write FFH after the clear lock-bits operation to place device in read array mode. Bus Operation Standby ...
Page 57
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Figure 24: Protection Register Programming Flowchart Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register No SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE ...
Page 58
... Type/ maximum device bus Mode width addresses x16 device 10h x16 mode x16 device Datasheet 58 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Query data with maximum device bus width addressing Hex ASCII Hex Code Offset Value 10: 0051 “ ...
Page 59
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Table 35: Summary of Query Structure Output as a Function of Device and Mode Device Query start location in Type/ maximum device bus Mode width addresses (1) x8 mode N/A Note: 1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is " ...
Page 60
... BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is 128 KB). 3. Offset 15 defines “P” which points to the Primary Numonyx-Specific Extended Query Table. 13.3 Block Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations ...
Page 61
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 13.5 System Interface Information The following device information can optimize system interface software. Table 40: System Interface Information Offset Length V logic supply minimum program/erase voltage CC 1Bh 1 bits 0–3 BCD 100 mV bits 4–7 BCD volts ...
Page 62
... Primary extended query table (P+1)h Unique ASCII string “PRI” (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII Datasheet 62 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Description 32 Mbit 64 Mbit --16 --17 --02 --02 --00 --00 --05 --05 --00 --00 ...
Page 63
... Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Table 43: Primary Vendor-Specific Extended Query (Sheet (1) Offset Length P = 31h (Optional Flash Features and Commands) 4 Optional feature and command support (1=yes, 0=no) Undefined bits are “0.” If bit 31 is “1” then another 31 bit field of optional features follows at the end of the bit-30 field ...
Page 64
... J3C mark for VIL fix for customers Note: 1. The variable pointer which is defined at CFI offset 15h. Datasheet 64 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Description (Optional Flash Features and Commands factory pre-programmed bytes n = user-programmable bytes Description ...
Page 65
... AP-646 Common Flash Interface (CFI) and Command Sets 319942 Numonyx Note: Contact your local Numonyx or distribution sales office or visit the Numonyx home page technical documentation, tools, or the most current information on Numonyx Single Bit per Cell (SBC) . March 2010 208032-02 Document/Tool ® ...
Page 66
... PC28F320J3F75* Datasheet 66 ® Numonyx Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC 64-Mbit JS28F640J3F75* RC28F640J3F75* PC28F640J3F75* Device Features * Access Speed 75ns Lithography F = 65nm Voltage ( PEN V/3 V Product Family ® Numonyx Embedded Flash Memory 128-Mbit JS28F128J3F75* RC28F128J3F75* PC28F128J3F75* March 2010 208032-02 ...