MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet - Page 13

MT45W8MW16BGX-701 IT

Manufacturer Part Number
MT45W8MW16BGX-701 IT
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT45W8MW16BGX-701 IT

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
Burst Mode Operation
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
Burst mode operations enable high-speed synchronous READ and WRITE operations.
Burst operations consist of a multi-clock sequence that must be performed in an
ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge
of the next clock that ADV# is LOW. During this first clock rising edge, WE# indicates
whether the operation is going to be a READ (WE# = HIGH, in Figure 8 on page 14) or
WRITE (WE# = LOW, in Figure 9 on page 14).
The size of a burst can be specified in the BCR either as a fixed length or as continuous.
Fixed-length bursts consist of four, eight, sixteen, or thirty-two words. Continuous
bursts have the ability to start at a specified address and burst to the end of the 128-word
row.
The latency count stored in the BCR defines the number of clock cycles that elapse
before the initial data value is transferred between the processor and CellularRAM
device. The initial latency for READ operations can be configured as fixed or variable
(WRITE operations always use fixed latency). Variable latency enables the CellularRAM
to be configured for minimum latency at high clock frequencies, but the controller must
monitor WAIT to detect any conflict with refresh cycles.
Fixed latency outputs the first data word after the worst-case access delay, including
allowance for refresh collisions. The initial latency time and clock speed determine the
latency count setting. Fixed latency is used when the controller cannot monitor WAIT.
Fixed latency also provides improved performance at lower clock frequencies.
The WAIT output asserts when a burst is initiated and de-asserts to indicate when data is
to be transferred into (or out of ) the memory. WAIT will again be asserted at the
boundary of the 128-word row unless wrapping within the burst length.
To access other devices on the same bus without the timing penalty of the initial latency
for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK.
CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst
is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise,
OE# can remain LOW. Note that the WAIT output will continue to be active, and as a
result, no other devices should directly share the WAIT connection to the controller. To
continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is
available on the bus.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than
CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW
cycle.
t
CEM. If a burst suspension will cause CE# to remain LOW for longer than
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
©2004 Micron Technology, Inc. All rights reserved.
t
CEM,

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