MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet - Page 27

• Manufacturer Part Number: MT45W8MW16BGX-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
Figure 19:
Figure 20:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
WAIT Configuration (BCR[8] = 0)
WAIT Configuration (BCR[8] = 1)
Notes:
Notes:
The WAIT configuration bit is used to determine when WAIT transitions between the
asserted and the de-asserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during
synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid
on the clock edge immediately after WAIT transitions to the de-asserted or asserted
state, respectively. (See Figures 19 and 21.) When BCR[8] = 1, the WAIT signal transitions
one clock period prior to the data bus going valid or invalid. (See Figures 20 and 21.)
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state.
DQ[15:0]
1. Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). (See Figure 21.)
DQ[15:0]
1. Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). (See Figure 21.)
WAIT
WAIT
CLK
CLK
Data valid (or invalid) after one clock delay
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
High-Z
Data immediately valid (or invalid)
High-Z
Data 0
Data 1
Data 0
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Page/Burst CellularRAM 1.5 Memory
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