MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet - Page 32

• Manufacturer Part Number: MT45W8MW16BGX-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Table 7:
DPD (RCR[4]) Default = DPD Disabled
Page Mode Operation (RCR[7]) Default = Disabled
Device Identification Register (DIDR)
Table 8:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
Bit Field
Field name
Meaning
Bit setting
RCR[2]
0
0
0
0
1
1
1
1
RCR[1]
128Mb Address Patterns for PAR (RCR[4] = 1)
Device Identification Register Mapping
0
0
1
1
0
0
1
1
Notes:
Row length
128 words
DIDR[15]
RCR[0]
0b
0
1
0
1
0
1
0
1
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150µs to perform an initialization proce-
dure before normal operations can resume.
Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD can be
enabled using CRE or the software sequence to access the RCR. Taking CE# LOW for at
least 10µs disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable
DPD. BCR and RCR values (other than BCR[4]) are preserved during DPD.
The page mode operation bit determines whether page mode is enabled for asynchro-
nous READ operations. In the power-up default state, page mode is disabled.
The DIDR provides information on the device manufacturer, CellularRAM generation,
and the specific device configuration. Table 8 describes the bit fields in the DIDR. This
register is read-only.
The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access
software sequence with DQ = 0002h on the third cycle.
1. Vendors with 256-word row lengths for CellularRAM 1.5 devices will set DIDR[15] to 1b.
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
One-quarter of die
One-quarter of die
One-eighth of die
One-eighth of die
Active Section
One-half of die
One-half of die
Bit setting Version
None of die
0000b
0001b
0010b
Device version
(etc.)
Full die
DIDR[14:11]
(etc.)
2nd
3rd
1st
32
Device density
DIDR[10:8]
000000h–7FFFFFh
000000h–3FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
400000h–7FFFFFh
600000h–7FFFFFh
700000h–7FFFFFh
Address Space
128Mb
011b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Page/Burst CellularRAM 1.5 Memory
0
CellularRAM 1.5
CellularRAM
generation
DIDR[7:5]
010b
8 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
Size
©2004 Micron Technology, Inc. All rights reserved.
DIDR[4:0]
Vendor ID
00011b
Micron
Density
128Mb
16Mb
16Mb
64Mb
32Mb
64Mb
32Mb
0Mb