MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet - Page 38

• Manufacturer Part Number: MT45W8MW16BGX-701 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W8MW16BGX-701 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Table 15:
PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65
128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN
Parameter
Address access time (fixed latency)
ADV# access time (fixed latency)
Burst to READ access time (variable latency)
CLK to
output delay
Address hold from ADV# HIGH (fixed
latency)
Burst OE# LOW to output delay
CE# HIGH between subsequent burst or
mixed-mode operations
Maximum CE# pulse width
CE# LOW to WAIT valid
CLK period
Chip select access time (fixed latency)
CE# setup time to active CLK edge
Hold time from active CLK Edge
Chip disable to DQ and WAIT High-Z output
CLK rise or fall time
CLK to WAIT
valid
Output hold from CLK
CLK HIGH or LOW time
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
Burst READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of one-half drive strength (BCR[5:4] = 01b).
Variable LC = 4
Fixed LC = 8
All other LCs
Variable LC = 4
Fixed LC = 8
All other LCs
Notes:
1. Values are valid for
2. A refresh opportunity must be provided every
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 36. The
4. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 36. The
-708, and -856.
either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than
15ns.
High-Z timings measure a 100mV transition from either V
Low-Z timings measure a 100mV transition away from the High-Z (V
either V
128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/
OH
or V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AA
AADV
ABA
ACLK
AVH
BOE
CBPH
CEM
CEW
CLK
CO
CSP
HD
HZ
KHKL
KHTL
KOH
KP
OHZ
OLZ
SP
OL
.
t
CLK (MIN) with no refresh collision: LC= 4 for -7013; LC = 3 for -701,
(133 MHz)
Min Max Min Max Min Max Min
7.5
2.5
1.5
2
5
1
2
3
3
2
-7013
38
35.5
5.5
7.5
1.2
5.5
70
70
20
70
7
4
7
7
7
(104 MHz)
9.62
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
5
1
3
2
2
3
3
3
Page/Burst CellularRAM 1.5 Memory
-701
35.9
7.5
1.6
70
70
20
70
7
7
4
8
7
7
8
t
CEM. A refresh opportunity is satisfied by
12.5
(80 MHz)
4
2
2
6
1
2
4
3
3
-708
46.5
OH
7.5
1.8
70
70
20
70
9
9
4
8
9
9
8
or V
©2004 Micron Technology, Inc. All rights reserved.
OL
(66 MHz)
15
2
8
1
5
2
2
5
3
3
-856
toward V
CC
Q/2) level toward
Max
7.5
2.0
85
85
55
11
11
20
85
11
11
4
8
8
CC
Unit Notes
Q/2.
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
2
4
3
4