MT18VDDF12872G40BC3 Micron Technology Inc, MT18VDDF12872G40BC3 Datasheet - Page 13

• Manufacturer Part Number: MT18VDDF12872G40BC3
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872G40BC3

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.8A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Not Compliant

Register and PLL Specifications
Table 12:
PDF: 09005aef807eb17d/Source: 09005aef807d24c9
ddf18c64_128x72d.fm - Rev. D 10/08 EN
Parameter
DC high-level
input voltage
DC low-level
input voltage
AC high-level
input voltage
AC low-level
input voltage
Output high voltage
Output low voltage
Input current
Static standby
Static operating
Dynamic operating
(clock tree)
Dynamic operating
(per each input)
Input capacitance
(per device, per pin)
Input capacitance
(per device, per pin)
Register Specifications
SSTV16859 devices or equivalent JESD82-4B
Notes:
Symbol
V
V
V
V
I
I
IH
IH
V
IL
IL
V
I
I
DDD
DDD
DD
DD
C
C
OH
(
(
I
OL
(
(
I
DC
AC
DC
AC
I
I
1. Timing and switching specifications for the register listed above are critical for proper oper-
)
)
)
)
ation of the DDR SDRAM RDIMM devices. These are meant to be a subset of the parameters
for the specific device used on the module. Detailed information for this register is available
in JEDEC Standard JESD82.
command, address
command, address
command, address
command, address
All inputs except
Parity output
Parity output
Control,
Control,
Control,
Control,
All pins
All pins
All pins
RESET#
RESET#
Pins
n/a
n/a
512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
switching 50% duty cycle;
One data input switching
switching 50% duty cycle
at
RESET# = V
V
V
V
I
I
t
I
I
V
I
V
V
CK/2, 50% duty cycle
O
O
= V
= V
= V
I
I
RESET# = V
I
RESET# = V
RESET# = V
= 0; CK and CK#
= 0; CK and CK#
= V
= V
= V
13
V
Condition
IH
IH
DD
IH
LVCMOS
LVCMOS
SSTL_25
SSTL_25
SSTL_25
SSTL_25
(
(
DD
REF
DD
(
I
AC
AC
Q = 1.8V
AC
O
Q or V
Q or V
= 0
) or V
) or V
SS
) or V
±250mV;
Q (I
SS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
IL
IL
Q;
O
IL
SS
SS
,
(
,
(
(
AC
AC
Q
= 0)
Q
DC
),
),
)
Register and PLL Specifications
V
V
REF
REF
V
DD
(
(
Min
DC
DC
–5.0
2.5
–
–
–
–
–
–
–
–
- 0.2
) + 150
) + 310
©2004 Micron Technology, Inc. All rights reserved
manufacturer
manufacturer
manufacturer
manufacturer
V
V
REF
REF
Varies by
Varies by
Varies by
Varies by
(
(
Max
+5.0
V
DC
DC
100
0.2
3.5
–
DD
–
) - 150
) - 310
Units
mV
mV
mV
mV
mA
µA
µA
µA
µA
pF
pF
V
V