MT18VDDF12872G40BC3 Micron Technology Inc, MT18VDDF12872G40BC3 Datasheet - Page 15

• Manufacturer Part Number: MT18VDDF12872G40BC3
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872G40BC3

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.8A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Not Compliant

Serial Presence-Detect
Table 15:
Table 16:
Serial Presence-Detect Data
PDF: 09005aef807eb17d/Source: 09005aef807d24c9
ddf18c64_128x72d.fm - Rev. D 10/08 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current: SCL = SDA = V
V
Power supply current: SCL clock frequency = 100 kHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA fall time
SDA rise time
Data-in hold time
Start condition hold time
Clock HIGH period
Clock LOW period
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
DD
Serial Presence-Detect EEPROM DC Operating Conditions
Serial Presence-Detect EEPROM AC Operating Conditions
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
DD
- 0.3V; All other inputs = V
DD
DD
512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
15
SS
or
t
WRC) is the time from a valid stop condition of a write
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
Symbol
t
t
t
t
HD:DAT
V
t
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
HD:DI
t
HIGH
LOW
f
WRC
DDSPD
t
V
BUF
V
SCL
V
I
I
AA
I
t
I
t
LO
SB
CC
OL
R
LI
F
IH
IL
V
DDSPD
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
–
–
0
–
–
Min
–1.0
2.3
–
–
–
–
–
× 0.7
Serial Presence-Detect
Max
300
300
400
0.9
©2004 Micron Technology, Inc. All rights reserved
–
–
–
–
–
–
–
–
–
5
V
V
DDSPD
DDSPD
Max
3.6
0.4
2.0
10
10
30
Units
kHz
+ 0.5
× 0.3
ms
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
µs
µs
Notes
Units
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4