MR2A08AMYS35 EverSpin Technologies Inc, MR2A08AMYS35 Datasheet

Page 1

FEATURES • + 3.3 Volt power supply • Fast 35ns read/write cycle • SRAM compatible timing • Unlimited read & write endurance • Data always non-volatile for >20-years at temperature • RoHS-compliant TSOPII package • AEC-Q100 Grade 1 Automotive Temperature (-40 to +125 °C) BENEFITS • One memory replaces FLASH, SRAM, EEPROM and BBSRAM in system for simpler, more efficient designs • Improves reliability by replacing battery-backed SRAM • Automatic data protection on power loss INTRODUCTION The MR2A08AM is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as 524,288 words of 8 bits. The MR2A08AM offers SRAM compatible 35ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR2A08AM is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR2A08AM is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP type-II package which is compatible with similar low-power SRAM products and other non-volatile RAM products. The MR2A08AM provides highly reliable data storage over a wide range of temperatures. The product is offered in AEC-Q100 grade 1 automotive temperature (-40 to +125 °C) range options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 7 4. ORDERING INFORMATION....................................................................... 11 ...

Page 2

DEVICE PIN ASSIGNMENT OUTPUT G ENABLE BUFFER 9 A[18:0] ADDRESS 10 BUFFER 19 CHIP E ENABLE BUFFER WRITE W ENABLE BUFFER Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O V Power Supply DD V ...

Page 3

DEVICE PIN ASSIGNMENT Figure 1.2 Pin Diagrams for Available Packages (Top View high low don’t care 1 Hi-Z = high impedance 2 Everspin Technologies © 2011 ...

Page 4

ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Parameter Supply voltage 2 Voltage on an pin 2 Output current per pin Package power dissipation Temperature under bias Storage Temperature Lead temperature during solder (3 minute max) Maximum magnetic field during write Maximum magnetic field during read or standby Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera- 1 tion should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. All voltages are referenced Power dissipation capability depends on package characteristics and use environment. 3 Everspin Technologies © 2011 Table 2.1 Absolute Maximum Ratings Symbol ...

Page 5

Electrical Specifications Parameter Power supply voltage Write inhibit voltage Input high voltage Input low voltage Temperature under bias iv There startup time once (max 0 (max (min (min) = -2.0 V iii Automotive temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life) iv Power Up and Power Down Sequencing MRAM is protected from write operations whenever V there is a startup time before read or write operations can start. This time allows memory power ...

Page 6

Electrical Specifications Parameter Input leakage current Output leakage current Output low voltage ( mA +100 μA) OL Output high voltage ( mA -100 μA) OL Parameter AC active supply current - read modes ( mA max) OUT DD AC active supply current - write modes (V = max standby current (V = max other restrictions on ...

Page 7

TIMING SPECIFICATIONS Parameter Address input capacitance Control input capacitance Input/Output capacitance f = 1.0 MHz 3 °C, periodically sampled rather than 100% tested Parameter Logic input timing measurement reference level Logic output timing measurement reference level Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters Output load for all other timing parameters Output Everspin Technologies © 2011 Table 3.1 Capacitance Symbol Table 3.2 AC Measurement Conditions Figure 3.1 Output Load Test Low and ...

Page 8

Timing Specifications Read Mode Parameter Read cycle time Address access time Enable access time 2 Output enable access time Output hold from address change Enable low to output active 3 Output enable low to output active Enable high to output Hi-Z 3 Output enable high to output Hi high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be 1 minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. 2 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage (ADDRESS) Q (DATA OUT) Note: Device is continuously selected (E≤V A (ADDRESS) E (CHIP ENABLE) ...

Page 9

Timing Specifications Parameter Write cycle time 2 Address set-up time G Address valid to end of write ( G Address valid to end of write ( G Write pulse width ( high) G Write pulse width ( low) Data valid to end of write Data hold time Write low to data Hi-Z 3 Write high to output active 3 Write recovery time All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. 2 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given 3 voltage or temperate, t (max) < t WLQZ A (ADDRESS) E (CHIP ...

Page 10

Timing Specifications Parameter Write cycle time 2 Address set-up time G Address valid to end of write ( G Address valid to end of write ( G Enable to end of write ( high) G Enable to end of write ( low) Data valid to end of write Data hold time Write recovery time All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address goes low at the same time or after W goes low, the output will remain in a high-impedance state goes high at the 3 same time or before W goes high, the output will remain in a high-impedance state. A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D ...

Page 11

... ORDERING INFORMATION Part Number MR2A08AMYS35 MR2A08AMYS35R Everspin Technologies © 2011 Figure 4.1 Part Numbering System Table 4.1 Available Parts Description 3.3 V 512Kx8 MRAM 44-TSOP 3.3 V 512Kx8 MRAM 44-TSOP T&R 11 Document Number: MR2A08AM Rev. 0, 2/2011 MR2A08AM Carrier (Blank = Tray Tape & Reel) Speed (35 ns) Package (YS = TSOPII) Temperature Range (M= -40 to +125 °C) ...

Page 12

MECHANICAL DRAWING 1. Dimensions and tolerances per ASME Y14.5M - 1994. 2. Dimensions in Millimeters. 3. Dimensions do not include mold protrusion. 4. Dimension does not include DAM bar protrusions. DAM Bar protrusion shall not cause the lead width to exceed 0.58. Everspin Technologies © 2011 Figure 5.1 TSOP-II Print Version Not To Scale 12 Document Number: MR2A08AM Rev. 0, 2/2011 MR2A08AM ...

Page 13

REVISION HISTORY Revision Date 0 Feb 28, 2011 Initial Release from original MR2A08A datasheet. Unless otherwise noted, this is a Production Product - This product conforms to specifications per the terms of the Everspin standard warranty. The product has completed Everspin internal qualification testing and has reached production status. How to Reach Us: Home Page: www.everspin.com E-Mail: support@everspin.com orders@everspin.com sales@everspin.com USA/Asia/Pacific Everspin Technologies 1300 N. Alma School Road, CH-409 Chandler, Arizona 85224 +1-877-347-MRAM (6726) +1-480-347-1111 Europe, Middle East and Africa support.europe@everspin.com Wokingham, United Kingdom +44 (0)118 907 6155 Japan support.japan@everspin.com Yokohama, ...