W83627THF Nuvoton Technology Corporation of America, W83627THF Datasheet

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W83627THF

Manufacturer Part Number
W83627THF
Description
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83627THF

Pin Count
128
Lead Free Status / RoHS Status
Not Compliant

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W83627THF
W83627THG
Winbond LPC I/O
Date:
Sep. 26, 2006
Revision: 1.22

Related parts for W83627THF

W83627THF Summary of contents

Page 1

... W83627THF W83627THG Winbond LPC I/O Date: Sep. 26, 2006 Revision: 1.22 ...

Page 2

... W83627THF/W83627THG Data Sheet Revision History PAGES DATES 1 N.A. 01/16/2003 P.104 2 03/25/2003 P.117~120 3 P.116~122 04/10/2003 P.7 4 08/05/2003 P.18 5 P.8 02/16/2004 6 03/09/3002 7 P.116 07/22/04 8 11/09/04 9 P.19 01/19/05 10 P.8 04/13/05 11 P.8 09/26/2006 W83627THF/W83627THG WEB VERSION VERSION 0.50 First published preliminary version. SUSLED data correction. ...

Page 3

... Voltage SMI# mode : .......................................................................................................................31 5.6.2 Fan SMI# mode : .............................................................................................................................31 5.6.3 The W83627THF temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes: .............................32 5.6.4 The W83627THF temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. ...........................................................................................33 5.7 OVT# interrupt mode.............................................................................................................. 34 ...

Page 4

... AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) ......................53 5.8.41 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) ..........53 5.8.42 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2)...........54 W83627THF/W83627THG Publication Release Date: September 26, 2006 - III - ...

Page 5

... AUXFANOUT Stop Time Register -- Index 17h (Bank 0) ................................................................70 5.8.82 VRM & OVT Configuration Register -- Index 18h (Bank 0)..............................................................71 5.8.83 Reserved -- Index 19h (Bank 0).......................................................................................................72 5.8.84 User Defined Register -- Index 1A- 1Bh (Bank 0) ............................................................................72 5.8.85 Reserved Register-- Index 1Ch-1Fh (Bank 0) .................................................................................72 6. PLUG AND PLAY CONFIGURATION ............................................................................................. 73 W83627THF/W83627THG - IV - ...

Page 6

... PACKAGE DIMENSIONS .............................................................................................................. 110 12. APPENDIX A : DEMO CIRCUIT .................................................................................................... 111 13. W83627THF VERSION CHANGE NOTICE 1................................................................................ 118 14. W83627THF APPLICATION NOTICE 4 (FOR E VERSION) ...................................................... 119 14.1 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h ....................... 121 14.2 SYSFANOUT Output Value Select Register - Index 01h .................................................... 122 14.3 CPUFANOUT PWM Output Frequency Configuration Register - Index 02h....................... 123 14 ...

Page 7

... AUXFANOUT Output Value Select Register - Index 11h .................................................... 131 14.16 FAN Configuration Register II - Index 12h ........................................................................... 132 14.17 AUXFANOUT Stop Value Register - Index 15h................................................................... 133 14.18 AUXFANOUT Start-up Value Register - Index 16h ............................................................. 133 14.19 AUXFANOUT Stop Time Register - Index 17h.................................................................... 134 W83627THF/W83627THG - VI - ...

Page 8

... ROM and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEY TM Phoenix MultiKey/ customer code. The W83627THF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. W83627THF/W83627THG ...

Page 9

... Moreover, W83627THF is made to meet the specification of PC2001's requirement in the power management: ACPI 1.0/1.0b/2.0 and DPM (Device Power Management). The W83627THF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices. They are very important for an entertainment or consumer computer ...

Page 10

... Support 3-mode FDD, and its Win95/98/NT/2K/XP driver UART Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1 stop bits generation W83627THF/W83627THG Publication Release Date: September 26, 2006 - 3 - Revision 1.2 ...

Page 11

... Support both interrupt and polling modes Fast Gate A20 and Hardware Keyboard Reset 8 Bit Timer/ Counter Support binary and BCD arithmetic 6 MHz, 8 MHz, 12 MHz MHz operating frequency Game Port Support two separate Joysticks Support every Joystick two axis (X, Y) and two button (A, B) controllers W83627THF/W83627THG - 4 - ...

Page 12

... WATCHDOG comparison of all monitored values Programmable hysteresis and setting points for all monitored items Over temperature indicate output Issue SMI#, IRQ, OVT# to activate system protection Winbond Hardware DoctorTM Support Intel LDCMTM compatible Package 128-pin PQFP W83627THF/W83627THG Publication Release Date: September 26, 2006 - 5 - Revision 1.2 ...

Page 13

... BLOCK DIAGRAM FOR 627THF LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface signals MSI MSO General-purpose I/O pins Hardware monitor channel and Vref Keyboard/Mouse data and clock W83627THF/W83627THG LPC Interface Game FDC Port MIDI URA, B GPIO IR HM PRT KBC ACPI - 6 - Floppy drive ...

Page 14

... PIN CONFIGURATION FOR 627THF Note: Please refer to Section 8.2 DC CHARACTERISTICS for details. W83627THF/W83627THG Publication Release Date: September 26, 2006 - 7 - Revision 1.2 ...

Page 15

... O Output pin with 24 mA source-sink capability 24 O 3.3V output pin with 12 mA source-sink capability 12p3 O 3.3V output pin with 24 mA source-sink capability 24p3 OD Open-drain output pin with 12 mA sink capability 12 OD Open-drain output pin with 24 mA sink capability 24 W83627THF/W83627THG DESCRIPTION - 8 - ...

Page 16

... IN LFRAME# 29 tsp3 IN LRESET# 30 tsp3 W83627THF/W83627THG DESCRIPTION FUNCTION System clock input. According to the input frequency 24MHz or 48MHz selectable through register. Default is 24MHz input. erated P PCI 33 MHz clock input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral ...

Page 17

... OD 24 DSKCHG W83627THF/W83627THG FUNCTION Drive Density Select bit 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN) ...

Page 18

... INIT AFD W83627THF/W83627THG FUNCTION PRINTER MODE: An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. PRINTER MODE: An active high input on this pin indicates that the printer has detected the end of the paper ...

Page 19

... PD6 36 12t I/O PD7 35 12t W83627THF/W83627THG FUNCTION PRINTER MODE: STB# An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD0 Parallel port data bus bit 0. ...

Page 20

... SOUTA 54 I/O8t PENKBC W83627THF/W83627THG FUNCTION Clear To Send the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Clear To Send the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register ...

Page 21

... CASE OPEN. An active low input from an external device when case is opened. This signal can be latched if pin VBAT is t connect to battery, even W83627THF is power off 4.096V FSR Analog Inputs 4.096V FSR Analog Inputs 4.096V FSR Analog Inputs 4.096V FSR Analog Inputs. ...

Page 22

... GP17 I/OD 12cs 3.8 General Purpose I/O Port 3.8.1 General Purpose I/O Port 1 (Power source is Vcc) see 3.7 Game Port W83627THF/W83627THG Temperature sensor 1 input used for system temperature maturation. Over temperature Shutdown 12 temperature is over temperature limit +5V amplitude fan tachometer input. ...

Page 23

... I/OD GP37 24t 64 SUSLED/ OUT I/OD GP40 75 W83627THF/W83627THG General purpose I/O port 2 bit 0. MIDI serial data output. (Default) 12 IRQ channel input 0. General purpose I/O port 2 bit 1. MIDI serial data input internally pulled ohms resistor. (Default) General purpose I/O port 2 bit 2. (Default) General purpose I/O port 2 bit 3 ...

Page 24

... I/O GP55 105 12tp3 Note. The GPIO Port 5 could be used as VID input / output function for VRD10. W83627THF/W83627THG FUNCTION General purpose I/O port 4 bit 1. SLP_S3# input. (Default) General purpose I/O port 4 bit 2. This pin generates the PWRCTL# signal while the power failure. ...

Page 25

... GPIO port 1 GPIO port 2 GPIO port 3 GPIO port 4 GPIO port 5 W83627THF/W83627THG FUNCTION +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. +3.3V power supply for driving 3V on host interface. Analog VCC input. Internally supplier to all analog circuitry. ...

Page 26

... GENERAL PURPOSE I/O W83627THF provides 36 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 36 GP I/O ports are divided into five groups . The first and fifth groups are configured through control registers in logical device 7, the second group in logical device 8, and the third and forth groups in logical device 9 ...

Page 27

... GP I/O PORT DATA REGISTER GP3(VSB POWER) GP4(VSB POWER) GP5(VCC POWER) W83627THF/W83627THG REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 Table 4-2 Figure 4-1 ...

Page 28

... W83627THF uses LPC Bus to access which the ports address of low byte (bit2~bit0) are defined in the port 5h and 6h. The other higher bits of these ports are set by W83627THF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port ...

Page 29

... LPC Bus Port 5h Index Register Port 6h Data Register Figure 5-1 : LPC interface access diagram W83627THF/W83627THG Smart Fan Configuration Registers 00h-1Fh Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers 43h-44h Fan Divisor Register I 47h Monitor Value Registers 20h~3Fh Device ID ...

Page 30

... CPU Vcore voltage, +3.3V, battery(pin 74), AVCC(pin 114) and 5VSB voltage can directly connected to these analog inputs. The +12V voltage inputs should be reduced a factor with external resistors obtain the input range. As Figure 3.2 shows. V1 Positive Voltage Input V2 Negative Voltage Input R THM 10K@25 C, beta=3435K W83627THF/W83627THG AVCC Power Inputs VBAT 5VSB VIN1(+3.3V) CPUVCORE R1 VIN0 R2 ...

Page 31

... The W83627THF internal two serial resistors are 34K ohms and 51K ohms so that input voltage to ADC is 3V which is less than 4.096V of ADC maximum input voltage. The express equation can represent as follows ...

Page 32

... III D- is connected to AGND and the pin D+ is connected to temperature sensor pin in the W83627THF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied together to act as a thermal diode ...

Page 33

... That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, RPM, and count W83627THF/W83627THG R=30K,1% R=30K,1% C=3300pF C 2N3904 E D+ C=3300pF D- Figure 5-3 × Count × RPM Divisor × RPM × Count Divisor - 26 - VREF VTIN W83627THF CPUTIN AGND ...

Page 34

... Pull-up resister 4.7K Ohms Pin 112-113,5 14K~39K Fan Input W83627THFD 10K Output and Register Attenuator Pull-up resister < totem-pole output > 1K Pin 112-113,5 Fan Input W83627THFD 3.9V Zener Revision 1.2 ...

Page 35

... Fan speed control The W83627THF has a 4 bit DAC which produces volts DC output that provides maximum 3 sets for fan speed control. The analog output can be programmed in the Bank0 Index 01h, Index 03h and Index 11h. The default value is 0xFY,Y is reserved nibble, that is default output value The ...

Page 36

... Thermal Cruise mode There are maximum 3 pairs of Temperature/FANOUT control at this mode: SYSTIN with SYSFANOUT, CPUTIN with CPUFANOUT, AUXTIN with AUXFANOUT. At this mode, W83627THF provides the Smart Fan system which can control the fan speed automatically depend on current temperature to keep it with in a specific range. At first a wanted temperature and interval must be set (ex. 55 ° ...

Page 37

... Fan Speed Cruise mode There are 3 pairs of FANIN/FANOUT control at this mode: SYSFANIN with SYSFANOUT, CPUFANIN with CPUFANOUT, AUXFANIN with AUXFANOUT. At this mode, W83627THF provides the Smart Fan system which can control the fan speed automatically depend on current fan speeds to keep it with in a specific range. A wanted fan speed count and interval must be set (ex. 160 ± BIOS. ...

Page 38

... Status Register. (Figure 5-13 ) High limit Low limit SMI# * *Interrupt Reset when Interrupt Status Registers are read Figure 5-12 W83627THF/W83627THG Fan Count limit SMI Publication Release Date: September 26, 2006 - 31 - ...

Page 39

... The W83627THF temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes: (1) Comparator Interrupt Mode Setting the T (Temperature Hysteresis) limit to 127 ° C will set temperature sensor 1 SMI# to the HYST Comparator Interrupt Mode. Temperature exceeds T and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has ...

Page 40

... T HYST SMI# *Interrupt Reset when Interrupt Status Registers are read 5.6.4 The W83627THF temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. (1) Comparator Interrupt Mode Temperature exceeding T causes an interrupt and this interrupt will be reset by reading all the O Interrupt Status Register ...

Page 41

... Once the OVT# is activated by exceeding T above T , the OVT# will not be activated again.( Figure 5-19) HYST T HYST OVT# (Comparator Mode; default) OVT# (Interrupt Mode) W83627THF/W83627THG , then OVT# reset, and then temperature *Interrupt Reset when Temperature sensor registers are read Figure 5-19 ...

Page 42

... Reserved Address Pointer (Power On default 00h) (Power On default 0) A6 5.8.2 Data Port (Port x6h) Data Port: Power on Default Value Attribute: Size: Bit 7-0: Data to be read from written to RAM and Register. W83627THF/W83627THG Port x5h 00h Bit 6:0 Read/write , Bit 7: Reserved 8 bits ...

Page 43

... Bit 1: A one enables the SMI# Interrupt output. Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit. W83627THF/W83627THG 40h 03h Read/write ...

Page 44

... Interrupt Status Register 2 ⎯ Index 42h 5.8.5 Register Location: Power on Default Value Attribute: Size: 7 Bit 7: A one indicates that the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan W83627THF/W83627THG 41h 00h Read Only 8 bits ...

Page 45

... Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. SMI# Mask Register 2 ⎯ Index 44h 5.8.7 Register Location: Power on Default Value Attribute: Size: Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. W83627THF/W83627THG 43h FEh Read/Write 8 bits ...

Page 46

... Reserved 27h SYSTIN temperature sensor reading SYSFANIN reading 28h Note: This location stores the number of counts of the internal clock per revolution. CPUFANIN reading 29h Note: This location stores the number of counts of the internal clock per revolution. W83627THF/W83627THG Reserved Reserved Reserved Reserved ...

Page 47

... Note the number of counts of the internal clock for the Low Limit of the fan speed. 3E- 3Fh Reserved Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits. W83627THF/W83627THG DESCRIPTION - 40 - ...

Page 48

... ADC clock select 5.6 Khz. (22.5K/4) <5:4> ADC clock select 1.4Khz. (22.5K/16) <5:4> ADC clock select 0.35 Khz. (22.5K/64) Bit 3-2: These two bits should be set to 01h. The default value is 01h. Bit 1-0: Reserved. W83627THF/W83627THG 49h 03h bit<7:1> Read Only; bit<0> Read/Write 8 bits ...

Page 49

... CPUTIN OVT output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: Reserved. Bit 0: Reserved. 5.8.15 FAN IN/OUT and BEEP Control Register- Index 4Dh Register Location: Power on Default Value Attribute: Size: 7 W83627THF/W83627THG 4Ch 18h Read/Write 8 bits ...

Page 50

... Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select. Set to 0, select Bank0. Set to 1, select Bank1. Set to 2, select Bank2. W83627THF/W83627THG 4Eh 80h Read/Write 8 bits 6 ...

Page 51

... BEEP output. Write 0, disable BEEP output, which is default value. Bit 3: BEEP output control for AVCC(pin 114) if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. W83627THF/W83627THG 4Fh <15:0> = 5CA3h Read Only ...

Page 52

... Bit 3: BEEP output control for AUXFANIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 2-1: Reserved. Bit 0: BEEP output control for VIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. W83627THF/W83627THG ...

Page 53

... Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 4: Diode mode selection of temperature SYSTIN if index 5Dh bit1 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 3-0: Reserved W83627THF/W83627THG 58h 90h Read Only ...

Page 54

... Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. After set this bit from the monitored value will be updated to the VBAT reading value register after one monitor cycle time. Fan divisor table : BIT 2 BIT 1 BIT W83627THF/W83627THG 5Dh 00h Read/Write 8 bits EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved FANDIV1_B2 FANDIV2_B2 ...

Page 55

... Bit 7: Temperature <8:1> of CPUTIN sensor, which is high byte, means 1 5.8.30 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) Register Location: 51h Attribute: Read Only Size: 8 bits 7 Bit 7: Temperature <0> of CPUTIN sensor, which is low byte, means 0.5 Bit 6-0: Reserved. W83627THF/W83627THG ...

Page 56

... Bit 0: Read/Write - When set to 1 the sensor will stop monitor. 5.8.32 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) Register Location: Power on Default Value Attribute: Size Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. W83627THF/W83627THG 52h 00h 8 bits ...

Page 57

... Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 5.8.34 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1) Register Location: Power on Default Value Attribute: Size Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. W83627THF/W83627THG 54h 00h Read/Write 8 bits THYST< ...

Page 58

... Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 5.8.36 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2) Register Location: 50h Attribute: Read Only Size: 8 bits 7 Bit 7: Temperature <8:1> of sensor 2, which is high byte, means 1 W83627THF/W83627THG 56h 00h Read/Write 8 bits TOVF< ...

Page 59

... Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor. W83627THF/W83627THG ...

Page 60

... Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 5.8.41 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) Register Location: Power on Default Value Attribute: Size: W83627THF/W83627THG 53h 4Bh Read/Write 8 bits 54h ...

Page 61

... AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2) Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 5.8.43 Interrupt Status Register 3 -- Index 50h (BANK4) Register Location: Power on Default Value Attribute: Size: W83627THF/W83627THG 56h 00h Read/Write 8 bits 6 5 ...

Page 62

... Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt. 5.8.45 Reserved Register -- Index 52h (Bank 4) 5.8.46 BEEP Control Register 3-- Index 53h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 W83627THF/W83627THG 51h FFh Read/Write 8 bits ...

Page 63

... Register Location: Power on Default Value Attribute: Size Bit 7-0: CPUTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. W83627THF/W83627THG 54h 00h Read/Write 8 bits ...

Page 64

... Bit 4: SYSTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit value. Set 0, the temperature is in under the hysteresis value. Bit 3: AVCC Voltage Status. Set 1, the voltage of AVCC is over the limit value. Set 0, the voltage of AVCC is in the limit range. W83627THF/W83627THG 56h 00h Read/Write ...

Page 65

... Bit 0: VIN2 Voltage Status. Set 1, the voltage of VIN2 is over the limit value. Set 0, the voltage of VIN2 is in the limit range. 5.8.53 Real Time Hardware Status Register III -- Index 5Bh (Bank 4) Register Location: Power on Default Value Attribute: Size: W83627THF/W83627THG 5Ah 00h Read Only 8 bits 6 5 ...

Page 66

... VBAT reading. The reading is meaningless if EN_VBAT_MNT bit(CR5D 51h bit0) is not set. 52h Reserved 53h Reserved 54h 5VSB High Limit 55h 5VSB Low Limit. 56h VBAT High Limit 57h VBAT Low Limit W83627THF/W83627THG 5VSB_STS VBAT_STS TAR3 Reserved Reserved Reserved Reserved Reserved ...

Page 67

... Bit 7-4: SYSFANOUT voltage control. OUTPUT Voltage = If AVCC output voltage table is BIT 7 BIT 6 BIT 5 BIT Note . The accuracy of FANOUT voltage is +/- 0.16 V. W83627THF/W83627THG 01h FFh Read/Write 8 bits Reserved Reserved Reserved Reserved SYSFANOUT Value FANOUT AVCC * 16 OUTPUT BIT 7 BIT 6 VOLTAGE 1.56 ...

Page 68

... Note: See the Table 5-4 5.8.62 FAN Configuration Register I -- Index 04h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 Bit7-6: Reserved Bit5-4: CPUFANOUT mode control. Set 00, CPUFANOUT is as Manual Mode. (Default). Set 01, CPUFANOUT is as Thermal Cruise Mode. W83627THF/W83627THG 03h FFh Read/Write 8 bits ...

Page 69

... Bit7: Reserved. Bit6-0: SYSTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-0: SYSFANIN Target Speed. 5.8.64 CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register -- Index 06h (Bank 0) Register Location: Power on Default Value Attribute: Size: W83627THF/W83627THG 05h 00h Read/Write 8 bits Target Temperature / Target Speed ...

Page 70

... Power on Default Value Attribute: Size (1).When at Thermal Cruise mode: Bit7-4: Tolerance of CPUTIN Target Temperature. Bit3-0: Tolerance of SYSTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit7-4: Tolerance of CPUFANIN Target Speed. Bit3-0: Tolerance of SYSFANIN Target Speed. W83627THF/W83627THG Target Temperature / Target Speed 07h 00h Read/Write 8 bits 3 2 ...

Page 71

... CPUFANOUT Stop Value Register -- 09h (Bank 0) Register Location: Power on Default Value Attribute: Size When at Thermal Cruise mode, CPUFANOUT voltage will decrease to this register value. This register should be written a non-zero minimum output value. W83627THF/W83627THG 08h 01h Read/Write 8 bits ...

Page 72

... CPUFANOUT Start-up Value Register -- Index 0Bh (Bank 0) Register Location: Power on Default Value Attribute: Size When at Thermal Cruise mode, CPUFANOUT voltage will increase from 0 to this register value to provide a minimum value to turn on the fan. W83627THF/W83627THG 0Ah 01h Read/Write 8 bits Reserved ...

Page 73

... When at Thermal Cruise mode, this register determines the time of which CPUFANOUT voltage is from stop value to 0. The unit of this register is 0.1 second. The default time is 6 seconds. 5.8.72 Fan Output Step Down Time Register -- Index 0Eh (Bank 0) Register Location: Power on Default Value Attribute: Size: W83627THF/W83627THG 0Ch 3Ch Read/Write 8 bits 5 4 ...

Page 74

... This register determines the speed of FANOUT increasing the voltage in Smart Fan Control mode. The Unit is 1.6 second 5.8.74 Reserved Register—Index10h (Bank 0) 5.8.75 AUXFANOUT Output Value Control Register-- 11h (Bank 0) Register Location: Power on Default Value Attribute: Size W83627THF/W83627THG FANOUT Value Step Down Time 0Fh 0Ah Read/Write ...

Page 75

... Set 01, AUXFANOUT is as Thermal Cruise Mode. Set 10, AUXFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 0:Reserved. 5.8.77 AUXTIN Target Temperature Register/ AUXFANIN Target Speed Register -- Index 13h (Bank 0) Register Location: Power on Default Value W83627THF/W83627THG FANOUT AVCC * 16 12h 00h Read/Write ...

Page 76

... Thermal Cruise mode: Bit3-0: Tolerance of AUXTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit3-0: Tolerance of AUXFANIN Target Speed. 5.8.79 AUXFANOUT Stop Value Register -- Index 15h (Bank 0) Register Location: Power on Default Value Attribute: Size: W83627THF/W83627THG Read/Write 8 bits Target Temperature / Target Speed ...

Page 77

... Size When at Thermal Cruise mode, AUXFANOUT value will increase from 0 to this register value to provide a minimum voltage to turn on the fan. 5.8.81 AUXFANOUT Stop Time Register -- Index 17h (Bank 0) Register Location: Power on Default Value Attribute: Size: W83627THF/W83627THG Reserved Reserved Reserved Reserved AUXFANOUT Stop Value ...

Page 78

... Bit 4: SYSTIN OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 3-1: Reserved. Bit 0: CPUVCORE pin voltage detection method selection. Set to 1, VRM9 formula is selected. Set to 0, VRM8 formula is selected. This bit default value is 1. W83627THF/W83627THG ...

Page 79

... Reserved -- Index 19h (Bank 0) 5.8.84 User Defined Register -- Index 1A- 1Bh (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 Bit 7-0: User can write any value into these bits and read. 5.8.85 Reserved Register-- Index 1Ch-1Fh (Bank 0) W83627THF/W83627THG 1A-1Bh FFh Read/Write 8 bits ...

Page 80

... PLUG AND PLAY CONFIGURATION The W83627THF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83627THF, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 ...

Page 81

... Extended Functions Enable Registers (EFERs) After a power-on reset, the W83627THF enters the default operating mode. Before the W83627THF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers ...

Page 82

... DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode ;------------------------------------------ MOV DX,2EH MOV AL,AAH OUT DX,AL W83627THF/W83627THG | | Publication Release Date: September 26, 2006 - Revision 1.2 ...

Page 83

... CR22 (Default 0xff) Bit ESERVED Bit 6 : HMPWD = 0 Power down = 1 No Power down Bit 5 : URBPWD = 0 Power down = 1 No Power down Bit 4 : URAPWD = 0 Power down = 1 No Power down Bit 3 : PRTPWD = 0 Power down = 1 No Power down Bit Reserved. Bit 0 : FDCPWD = 0 Power down = 1 No Power down W83627THF/W83627THG - 76 - ...

Page 84

... PnP registers if the present value of PNPCSV is 1. The corresponding power-on setting pin is NDTRA (pin 52). CR25 (Default 0x00) Bit Reserved Bit 5 : URBTRI Bit 4 : URATRI Bit 3 : PRTTRI Bit Reserved Bit 0 : FDCTRI. W83627THF/W83627THG When set will put the whole chip into power Publication Release Date: September 26, 2006 - 77 - Revision 1.2 ...

Page 85

... Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ CR28 (Default 0x00) Bit Reserved. Bit PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode W83627THF/W83627THG - 78 - ...

Page 86

... Winbond Test Mode . Bit 3 PIN95S GP24 Winbond Test Mode Bit 2 PIN94S GP25 Winbond Test Mode. Bit 1 PIN93S GP26 Winbond Test Mode Bit 0 PIN2S = 0 SMI IRQIN1 (select IRQ resource through CRF4 Bit 7-4 of Logical Device8). W83627THF/W83627THG Publication Release Date: September 26, 2006 - 79 - Revision 1.2 ...

Page 87

... Reserved. CR2C (GPIO3 multiplexed pin selection register 2. VSB powered. Default 0xssssss00b) Bit PIN91S1, PIN91S0 GP31 Reserved Reserved Reserved Bit PIN92S1, PIN92S0 GP30 Reserved Reserved Reserved Bit PIN64S1, PIN64S0 SUSLED GP37 Reserved Reserved. Bit 1 : PIN87S IRTX Winbond Test Mode. Bit 0 : Reserved. W83627THF/W83627THG - 80 - ...

Page 88

... CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8 byte boundary. W83627THF/W83627THG Publication Release Date: September 26, 2006 - 81 - Revision 1.2 ...

Page 89

... Swap Drive 0, 1 Mode = 0 No Swap (Default Drive and Motor select 0 and 1 are swapped. Bit :Interface Mode = 11 AT Mode (Default (Reserved PS Model 30 Bit 1 : FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0 : Floppy Mode = 0 Normal Floppy Mode (Default Enhanced 3-mode FDD W83627THF/W83627THG - 82 - ...

Page 90

... Reserved. Bit DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A Select Regular drives and 2.88 format = 01 3-mode drive = 10 2 Meg Tape = 11 Reserved Bit 2 : Reserved. Bit 1:0 : DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). W83627THF/W83627THG Publication Release Date: September 26, 2006 - 83 - Revision 1.2 ...

Page 91

... CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A DRIVE RATE TABLE SELECT DRTS1 DRTS0 TABLE B DTYPE0 DTYPE1 DRVDEN0(PIN W83627THF/W83627THG DATA RATE DRATE1 DRATE0 DRVDEN1(PIN 3) SELDEN DRATE0 DRATE1 DRATE0 DRATE0 SELDEN DRATE0 DRATE1 - 84 - SELECTED DATA RATE SELDEN MFM FM 1Meg --- 500K 250K ...

Page 92

... Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. W83627THF/W83627THG Publication Release Date: September 26, 2006 - 85 - Revision 1.2 ...

Page 93

... Bit These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit Reserved. Bit SUACLKB1, SUACLKB0 = 00 UART A clock source is 1.8462 Mhz (24MHz/13 UART A clock source is 2 Mhz (24MHz/12 UART A clock source is 24 Mhz (24MHz/ UART A clock source is 14.769 Mhz (24mhz/1.625) W83627THF/W83627THG - 86 - ...

Page 94

... CRF1 (Default 0x00) Bit 7 : Reserved. Bit 6 : IRLOCSEL. IR I/O pins' location select Through SINB/SOUTB Through IRRX/IRTX. Bit 5 : IRMODE2. IR function mode selection bit 2. Bit 4 : IRMODE1. IR function mode selection bit 1. Bit 3 : IRMODE0. IR function mode selection bit 0. W83627THF/W83627THG Publication Release Date: September 26, 2006 - 87 - Revision 1.2 ...

Page 95

... Inverse the SOUTB pin of UART B function or IRTX pin of IR function. Bit 0 : RX2INV The SINB pin of UART B function or IRRX pin of IR function in normal condition Inverse the SINB pin of UART B function or IRRX pin of IR function W83627THF/W83627THG IRTX tri-state Active pulse 1.6 μ S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & ...

Page 96

... Select 8MHz as KBC clock input Select 12Mhz as KBC clock input Select 16Mhz as KBC clock input. Bit Reserved. Bit Port 92 disable Port 92 enable. Bit Gate20 software control Gate20 hardware speed up. Bit KBRST software control KBRST hardware speed up. W83627THF/W83627THG Publication Release Date: September 26, 2006 - 89 - Revision 1.2 ...

Page 97

... If a port is programmed output port, then its respective bit can be read/written port is programmed input port, then its respective bit can only be read. CRF2 (GP1[7:0] inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. W83627THF/W83627THG - 90 - ...

Page 98

... When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 (Default 0x00) Bit These bits select IRQ resource for IRQIN1. Bit These bits select IRQ resource for IRQIN0. W83627THF/W83627THG Publication Release Date: September 26, 2006 - 91 - Revision 1.2 ...

Page 99

... Force Watch Dog Timer Time-out, Write only Force Watch Dog Timer time-out event; this bit is self-clearing. Bit 4 : Watch Dog Timer Status, R Watch Dog Timer time-out occurred = 0 Watch Dog Timer counting Bit These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI. W83627THF/W83627THG - 92 - ...

Page 100

... When set to a '0', respective GPIO port is programmed as an output port. CRF5 (GP4[7:0] data register. Default 0x00 port is programmed output port, then its respective bit can be read/written port is programmed input port, then its respective bit can only be read. W83627THF/W83627THG Publication Release Date: September 26, 2006 - 93 - Revision 1.2 ...

Page 101

... ENMDAT_UP MSRKEY Bit 3 Reserved Bit 2 : KB/MS Swap. Enable Keyboard/Mouse port-swap Keyboard/Mouse ports are not swapped Keyboard/Mouse ports are swapped. W83627THF/W83627THG MSXKEY WAKE UP EVENT x 1 Any button click or any movement x 0 one click of left/right button 0 1 one click of left button 1 1 one click of right button ...

Page 102

... Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is cleared by reading this register. Bit 0 : Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register. W83627THF/W83627THG MSXKEY WAKE UP EVENT x 1 Any button click or any movement ...

Page 103

... ENMDAT_UP MSRKEY Bit6 Chassis Status Clear = 1 Clear CASEOPEN# (Pin76) event Disable Clear Function. Bit Reserved W83627THF/W83627THG MSXKEY WAKE UP EVENT x 1 Any button click or any movement x 0 one click of left/right button 0 1 one click of left button 1 1 one click of right button ...

Page 104

... Bit 3 SELWDTORST: Select whether Watch Dog timer function is reset by LRESET_L signal or PWROK signal. =0 Watch Dog timer function is reset by LRESET_L signal. =1 Watch Dog timer function is reset by PWROK signal. Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved W83627THF/W83627THG Publication Release Date: September 26, 2006 - 97 - Revision 1.2 ...

Page 105

... Bit Devices' trap status. Bit 4 : Reserved. Return zero when read. Bit Devices' trap status. W83627THF/W83627THG - 98 - ...

Page 106

... PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or (HMIRQEN and HMIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (IRQIN3EN and IRQIN3STS) or (IRQIN2EN and IRQIN2STS) or (IRQIN1EN and IRQIN1STS) or (IRQIN0EN and IRQIN0STS) Bit 7 Reserved. Bit 6 Reserved W83627THF/W83627THG Publication Release Date: September 26, 2006 - 99 - Revision 1.2 ...

Page 107

... SMI / PME interrupt due to MIDI's IRQ enable the generation of an SMI / PME interrupt due to MIDI's IRQ. Bit 1 : IRQIN1EN disable the generation of an SMI / PME interrupt due to IRQIN1's IRQ enable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. W83627THF/W83627THG - 100 - ...

Page 108

... Logical device is inactive. CR60 (Default 0x00, 0x00) These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit Reserved. Bit These bits select IRQ channel for Hardware Monitor. W83627THF/W83627THG Publication Release Date: September 26, 2006 - 101 - Revision 1.2 ...

Page 109

... Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage IN - TTL level input pin t Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage W83627THF/W83627THG RATING -0.5 to 7.0 -0 2 +70 -55 to +150 = 0V) SS MIN. TYP MAX ...

Page 110

... Input High Threshold Voltage V Hystersis Input High Leakage Input Low Leakage IN - TTL level input pin with internal pull up resistor tu Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage pull up resistor W83627THF/W83627THG MIN. TYP MAX +10 LIH I -10 ...

Page 111

... Input High Leakage Input Low Leakage I/OD - TTL level bi-directional Schmitt-triggered pin. Open-drain output with 12 mA sink 12ts capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage W83627THF/W83627THG MIN. TYP MAX ...

Page 112

... Input High Leakage Input Low Leakage OD - Open-drain output pin with sink capability Output Low Voltage Open-drain output pin with sink capability Output Low Voltage Open-drain output pin with sink capability Output Low Voltage V W83627THF/W83627THG MIN. TYP MAX 2 +10 LIH I -10 ...

Page 113

... Output Low Voltage Output High Voltage OUT - TTL level output pin with source-sink capability Output Low Voltage Output High Voltage OUT - 3.3 V TTL level output pin with source-sink capability 12tp3 Output Low Voltage Output High Voltage W83627THF/W83627THG MIN. TYP MAX 0.4 ...

Page 114

... DCH2/PD4 18 RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram W83627THF/W83627THG DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2 RWC2 Publication Release Date: September 26, 2006 - 107 - JP 13A ...

Page 115

... STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram 9.3 Four FDD Mode W83977F DSA DSB MOA MOB W83627THF/W83627THG JP13 74LS139 G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 108 - JP 13A DCH2 34 33 HEAD2 32 ...

Page 116

... W83627THF 030A7C282012345UA 1st line: Winbond logo 2nd line: the type number: W83627THF, W83627THG (the “G” means Pb-free package) 3rd line: the tracking code 030A7C282012345UA 030: packages made in '00, week 30 A: assembly house ID; A means ASE, S means SPIL.... etc. ...

Page 117

... PACKAGE DIMENSIONS (128-pin QFP 102 103 128 See Detail F y Seating Plane W83627THF/W83627THG Detail F - 110 - Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom A 0.25 0.35 0.45 0.010 0.014 1 A 2.57 2.72 2.87 0.101 0.107 2 b 0.10 0.20 0.30 0.004 ...

Page 118

... PD0 PD1 PD[0..7] 4 PD2 PD3 PD4 PD5 PD6 PD7 ACK# 4 BUSY SLCT 4 |LINK |627THF_1.SCH |627THF_2.SCH |627THF_3.SCH |627THF_4.SCH |627THF_5.SCH |627THF_6.SCH |627THF_7.SCH Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size Document Number B W83627THF + FDC Date: Wednesday, April 09, 2003 Sheet 1 Revision 1.2 Rev 0 ...

Page 119

... J1 1 MDAT MCLK HEADER 6 47P 47P PS2 MOUSE VWAKE R5 R6 4.7K 4. KDAT KCLK C10 C11 HEADER 6 47P 47P 0.1U KEYBOARD Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size Document Number B GAME & MIDI & KBC Date: Wednesday, April 09, 2003 Sheet 2 Rev 0 ...

Page 120

... NDTRB 3 4 GND NDSRB 5 6 NRTSB NCTSB 7 8 NRIB 9 10 HEADER 5X2 COMB (UARTB) Publication Release Date: September 26, 2006 - 113 - CN2X5 Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size Document Number Rev B UART+IR 0.1 Date: Wednesday, April 09, 2003 Sheet Revision 1.2 ...

Page 121

... NDP2 2 NDP15 15 NDP3 3 16 NDP4 4 17 NDP5 5 18 NDP6 NDP10 10 23 NDP11 11 24 NDP12 12 25 NDP13 13 DB25 Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size Document Number Rev B PRINT PORT 0.1 Date: Wednesday, April 09, 2003 Sheet ...

Page 122

... Publication Release Date: September 26, 2006 - 115 - R?(8P4RA1 IOVSB IO5V 4 5 4.7K RP8 IO5V 4 5 4.7K I/O CONFIGURATION ADDRESS I/O PORT BASE DEFAULT VALUE PIN18 INPUT CLK VALUE W83627THF APPLICATION CIRCUIT Document Number Rev Power setting 0.1 Wednesday, April 09, 2003 Sheet Revision 1.2 ...

Page 123

... Note : 1. Transistor,MOSFET,LDO We suggest TO-252 or TO-262 type of package 2. Use 2SC5706, Max. FANVCC is 10.2V 3. Use CEB05P03, Max. FANVCC is 12V 4. Use LM1117, Max. FANVCC max is 10.8V Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size Document Number B FAN Control Date: Wednesday, April 09, 2003 Sheet FANIN2 ...

Page 124

... Publication Release Date: September 26, 2006 - 117 - IO5V R47 100 R48 4.7K LS1 SPEAKER Q5 BEEP NPN R50 IOBAT CASEOPEN SPST Winbond Electronic Corp. Title W83627THF APPLICATION CIRCUIT Size Document Number Rev B Temperature+Voltage sensing 0.1 Date: Wednesday, April 09, 2003 Sheet Revision 1.2 ...

Page 125

... W83627THF VERSION CHANGE NOTICE 1 Feature Brief W83627THF : LPC I/F + FDC + 2* UART + Parallel Port + KBC + Game Port + MIDI Port + ACPI + Power failure + Hardware Monitor + GPIO + VRD10.0 Description This version change notice is for the W83627THF to be changed from The contents: 1. The E version can directly replace C version without any circuit or S/W change except Fan Control Function ...

Page 126

... W83627THF APPLICATION NOTICE 4 (FOR E VERSION) Feature Brief W83627THF : LPC I/F + FDC + UART*2 + Parallel Port + KBC + Game Port + MIDI Port + ACPI + Power failure + Hardware Monitor + GPIO + VRD10.0 Description W83627THF Version E provides two controllable methods for Fan speed control. One is PWM duty cycle output and the other is DC voltage output. Either PWM or DC output can be programmed at CR[F0h] bit4 ~ bit6 of Logical Device B ...

Page 127

... DC Voltage Output The W83627THF has a 4 bit DAC which produces volts DC output that provides maximum 3 sets for fan speed control. The analog output can be programmed in the Bank0 Index 01h, Index 03h and Index 11h of H/W Monitor block. The default value is 0xFY,Y is reserved nibble, that is default output value is nearly 5V ...

Page 128

... PWM output frequency = W83627THF/W83627THG Fan speed control. Output analog voltage level to control the Fan's speed. Fan speed control. Use the Pulse Width Modulation (PWM) to control the Fan’s RPM. 00h 01h ...

Page 129

... Write 00h, SYSFANOUT is always logical Low which means duty cycle is 0%. Note. XXh: PWM Duty Cycle output percentage is (XX/255*100%) during one cycle. (2)If SYSFANOUT be programmed as DC Voltage output (CR[F0h bit4 is 0) Bit 7-4: SYSFANOUT voltage control. Bit 3-0: Reserved. OUTPUT Voltage = W83627THF/W83627THG 01h FFh Read/Write 8 bits 5 4 ...

Page 130

... Bit 7: CPUFANOUT PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. Bit 6-0: CPUFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. W83627THF/W83627THG OUTPUT BIT 7 VOLTAGE 0 0 ...

Page 131

... Note. XXh: PWM Duty Cycle output percentage is (XX/255*100%) during one cycle. (2)If CPUFANOUT be programmed as DC Voltage output (CR[F0h bit5 is 0) Bit 7-4: CPUFANOUT voltage control. Bit 3-0: Reserved. OUTPUT Voltage = Note. See the Table 7.4 W83627THF/W83627THG Input Pre_Scale 03h FFh Read/Write ...

Page 132

... Set 00, SYSFANOUT is as Manual Mode. (Default). Set 01, SYSFANOUT is as Thermal Cruise Mode. Set 10, SYSFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 1-0: Reserved. 14.6 SYSFANOUT Stop Value Register - Index 08h Register Location: Power on Default Value: Attribute: Size: W83627THF/W83627THG 04h 00h Read/Write 8 bits ...

Page 133

... CPUFANOUT Stop Value Register - Index 09h Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode, CPUFANOUT value will decreases to this register value. This register should be written a non-zero minimum stop value. W83627THF/W83627THG SYSFANOUT Stop Value 09h 01h Read/Write ...

Page 134

... CPUFANOUT Start-up Value Register - Index 0Bh Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode, CPUFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan. W83627THF/W83627THG 0Ah 01h Read/Write 8 bits SYSFANOUT Start-up Value ...

Page 135

... When at Thermal Cruise mode, this register determines the time of which CPUFANOUT value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 1.6 second. The default time is 96 seconds. W83627THF/W83627THG 0Ch 3Ch Read/Write 8 bits 4 ...

Page 136

... This register determines the speed of FANOUT increasing the its value in Smart Fan Control mode. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 1 seconds. (2)When at DC Voltage output: The unit of this register is 1.6 second. The default time is 16 seconds. W83627THF/W83627THG 0Eh 0Ah Read/Write 8 bits ...

Page 137

... Bit 6-0: AUXFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider the formula is W83627THF/W83627THG 10h 01h Read Only 8 bits ...

Page 138

... AUXFANOUT duty cycle is 0%. Note. XXh: PWM Duty Cycle output percentage is (XX/255*100%) during one cycle. (2)If AUXFANOUT be programmed as DC Voltage output CR[F0h bit6 is 0) Bit 7-4: AUXFANOUT voltage control. Bit 3-0: Reserved. OUTPUT Voltage = Note. See the Table 7.4 W83627THF/W83627THG 11h FFh Read/Write 8 bits 5 4 ...

Page 139

... Set 0, AUXFANOUT value will decrease to 0 when temperature goes below target range. Bit 2-1: AUXFANOUT mode control. Set 00, AUXFANOUT is as Manual Mode. (Default). Set 01, AUXFANOUT is as Thermal Cruise Mode. Set 10, AUXFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 0: Reserved. W83627THF/W83627THG 12h 00h Read/Write 8 bits 5 4 ...

Page 140

... AUXFANOUT Start-up Value Register - Index 16h Register Location: Power on Default Value: Attribute: Size When at Thermal Cruise mode, AUXFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan. W83627THF/W83627THG 15h 01h Read/Write 8 bits ...

Page 141

... The unit of this register is 1.6 second. The default time is 96 seconds. W83627THF/W83627THG Application Notice List DATE VERSION 1 03/01/10 APN1 2 03/04/08 APN2 3 04/01/16 APN3 4 09/26/2006 APN4 W83627THF/W83627THG 17h 3Ch Read/Write 8 bits AUXFANOUT Stop Time New release for W83627THF. For W83627THF C version W83627THF Power On Cycle Issue For W83627THF E version - 134 - REMARK ...

Page 142

... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83627THF/W83627THG Important Notice Publication Release Date: September 26, 2006 - 135 - ...

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