FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 328
FW82801EB S L73Z
Manufacturer Part Number
FW82801EB S L73Z
Description
Manufacturer
Intel
Datasheet
1.FW82801EB_S_L73Z.pdf
(671 pages)
Specifications of FW82801EB S L73Z
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LPC Interface Bridge Registers (D31:F0)
9.1.18
9.1.19
.
328
PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
D31_ERR_CFG—Device 31 Error Configuration Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
This register configures the ICH5’s Device 31 responses to various system errors. The actual
assertion of SERR# is enabled via the PCI Command register.
Bit
7:3
Bit
6:4
3:0
2
1
0
7
Reserved
SERR# on Received Target Abort Enable (SERR_RTA_EN) — R/W.
0 = Disable. No SERR# assertion on Received Target Abort.
1 = Enable. Intel
SERR# on Delayed Transaction Timeout Enable (SERR_DTT_EN) — R/W.
0 = Disable. No SERR# assertion on Delayed Transaction Timeout.
1 = Enable. ICH5 generates SERR# when SERR_DTT bit is set if SERR_EN is set.
Reserved
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The
Reserved
IRQ Routing — R/W. (ISA compatible.)
0000 = Reserved
0001 = Reserved
0010 = Reserved
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
value of this bit may subsequently be changed by the OS when setting up for I/O APIC
interrupt delivery mode.
PIRQE
PIRQG
80h
No
88h
00h
No
®
ICH5 generates SERR# when SERR_RTA is set if SERR_EN is set.
–
–
68h, PIRQF
6Ah, PIRQH
1000 = Reserved
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = IRQ12
1101 = Reserved
1110 = IRQ14
1111 = IRQ15
–
–
69h,
6Bh
Description
Intel
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
8 bit
Core
R/W
8 bit
Core
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