ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 16

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 3.
ISP1760_4
Product data sheet
Port configuration
One port (port 1)
One port (port 2)
One port (port 3)
Two ports (ports 1
and 2)
Two ports (ports 2
and 3)
Two ports (ports 1
and 3)
Three ports (ports 1,
2 and 3)
Port connection scenarios
7.2.1 General considerations
7.2 Host controller buffer memory block
Port 1
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
The internal addressable host controller buffer memory is 63 kB. The 63 kB effective
memory size is the result of subtracting the size of the registers (1 kB) from the total
addressable memory space defined in the ISP1760 (64 kB). This is the optimized value to
achieve the highest performance with minimal cost.
The ISP1760 is a slave host controller. This means that it does not need access to the
local bus of the system to transfer data from the system memory to the ISP1760 internal
memory, unlike the case of the original PCI Hi-Speed USB host controllers. Therefore,
correct data must be transferred to both the PTD area and the payload area by PIO (using
CPU access) or programmed DMA.
The ‘slave-host’ architecture ensures better compatibility with most of the processors
present in the market today because not all processors allow a ‘bus-master’ on the local
bus. It also allows better load balancing of the processor’s local bus because only the
internal bus arbiter of the processor controls the transfer of data dedicated to USB. This
prevents the local bus from being busy when other more important transfers may be in the
queue; and therefore achieving a ‘linear’ system data flow that has less impact on other
processes running at the same time.
The considerations mentioned are also the main reason for implementing the pre-fetching
technique, instead of using a READY signal. The resulting architecture avoids ‘freezing’ of
the local bus, by asserting READY, enhancing the ISP1760 memory access time, and
avoiding introduction of programmed additional wait states. For details, see
and
The total amount of memory allocated to the payload determines the maximum transfer
size specified by a PTD, a larger internal memory size results in less CPU interruption for
transfer programming. This means less time spent in context switching, resulting in better
CPU usage.
Section
8.3.8.
Rev. 04 — 4 February 2008
Port 2
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
Embedded Hi-Speed USB host controller
Port 3
DP and DM are not connected
(left open)
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
© NXP B.V. 2008. All rights reserved.
ISP1760
Section 7.3
15 of 110