ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 20

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
ISP1760_4
Product data sheet
7.3.2 PIO mode access, memory write cycle
7.3.3 PIO mode access, register read cycle
7.3.4 PIO mode access, register write cycle
7.3.5 DMA mode, read and write operations
The PIO memory write access is similar to a normal memory access. It is not necessary
to set the pre-fetching address before a write cycle to the memory.
The ISP1760 internal write address will not be automatically incremented during
consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The
memory write address must be incremented before every access.
The PIO register read access is similar to a general register access. It is not necessary to
set a pre-fetching address before a register read.
The ISP1760 register read address will not be automatically incremented during
consecutive read accesses, unlike in a series of ISP1760 memory read cycles. The
ISP1760 register read address must be correctly specified before every access.
The PIO register write access is similar to a general register access. It is not necessary to
set a pre-fetching address before a register write.
The ISP1760 register write address will not be automatically incremented during
consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The
ISP1760 register write address must be correctly specified before every access.
The internal ISP1760 host controller DMA is a slave DMA. The host system processor or
DMA must ensure the data transfer to or from the ISP1760 memory.
The ISP1760 DMA supports a DMA burst length of 1, 4, 8 and 16 cycles for both the 16-bit
and 32-bit data bus width. DREQ will be asserted at the beginning of the first burst of a
DMA transfer and will be de-asserted on the last cycle, RD_N or WR_N active pulse, of
that burst. It will be reasserted shortly after the DACK de-assertion, as long as the DMA
transfer counter was not reached. DREQ will be de-asserted on the last cycle when the
DMA transfer counter is reached and will not be reasserted until the DMA reprogramming
is performed. Both the DREQ and DACK signals are programmable as active LOW or
active HIGH, according to the system requirements.
– Write the starting (read) address 4100h and bank2 = 10 to the Memory register.
Remark: Once 4000h is written to the Memory register for bank1, the bank select
value determines the successive incremental addresses used to fetch data. That
is, the fetching of data is independent of the address on A[15:0] lines.
When RD_N is asserted for four cycles with A[17:16] = 10, the returned data
corresponds to addresses 4100h, 4104h, 4108h and 410Ch.
Consequently, the RD_N assertion with A[17:16] = 01 will return data from 400Ch
because the bank1 read stopped there in the previous cycle. Also, RD_N
assertions with A[17:16] = 10 will now return data from 4110h because the bank2
read stopped there in the previous cycle.
Rev. 04 — 4 February 2008
Embedded Hi-Speed USB host controller
© NXP B.V. 2008. All rights reserved.
ISP1760
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