ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 56

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 59.
Table 60.
Table 61.
Table 62.
ISP1760_4
Product data sheet
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0
Symbol
INT_IRQ_MASK
_OR[31:0]
Symbol
ISO_IRQ_MASK
_OR[31:0]
Symbol
ATL_IRQ_MASK
_OR[31:0]
Symbol
ISO_IRQ_MASK
_AND[31:0]
ISO IRQ Mask OR register (address 0318h) bit description
INT IRQ Mask OR register (address 031Ch) bit description
ATL IRQ Mask OR register (address 0320h) bit description
ISO IRQ Mask AND register (address 0324h) bit description
8.4.4 INT IRQ Mask OR register
8.4.5 ATL IRQ Mask OR register
8.4.6 ISO IRQ Mask AND register
8.4.7 INT IRQ Mask AND register
Each bit of this register (see
and is a hardware IRQ mask for each PTD done map. For details, see
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
see
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Table 62
Each bit of this register (see
and is a hardware IRQ mask for each PTD done map. For details, see
Access
R/W
Access
R/W
Section
Access Value
R/W
Access
R/W
provides the bit description of the register.
7.4.
0000 0000h
Value
0000 0000h ISO IRQ Mask OR: Represents a direct map for ISO PTDs 31 to 0.
Value
0000 0000h INT IRQ Mask OR: Represents a direct map for INT PTDs 31 to 0.
Value
0000 0000h ISO IRQ Mask AND: Represents a direct map for ISO PTDs 31 to 0.
Rev. 04 — 4 February 2008
Description
0 — No OR condition defined between ISO PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Description
0 — No OR condition defined between INT PTDs 31 to 0.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Description
ATL IRQ Mask OR: Represents a direct map for ATL PTDs 31 to 0.
0 — No OR condition defined between the ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Description
0 — No AND condition defined between ISO PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 INT PTDs.
Table
Table
60) corresponds to one of the 32 INT PTDs defined,
63) corresponds to one of the 32 INT PTDs defined,
Embedded Hi-Speed USB host controller
Table 61
for bit description. For details,
Section
7.4.
Section
Section
© NXP B.V. 2008. All rights reserved.
ISP1760
7.4.
7.4.
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