ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 76

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ISP1760ET,557

Manufacturer Part Number
ISP1760ET,557
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1760ET,557

Package Type
TFBGA
Pin Count
128
Lead Free Status / RoHS Status
Compliant
Table 75.
[1]
[2]
Bit
DW7
DW5
DW3
DW1
Bit
DW6
DW4
DW2
DW0
Reserved.
EndPt[0].
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Status7[2:0]
[2]
A
Start and complete split for isochronous: bit allocation
H
HubAddress[6:0]
[1]
9.5 Start and complete split for isochronous
B
ISO_IN_2[7:0]
ISO_IN_6[7:0]
reserved
Status6[2:0]
X
Table 75
SC
[1]
shows the bit allocation for start and complete split for isochronous, split isochronous Transfer Descriptor (siTD).
DT
Status5[2:0]
TT_MPS_Len[10:0]
PortNumber[6:0]
Status4[2:0]
ISO_IN_1[7:0]
ISO_IN_5[7:0]
reserved
Status3[2:0]
reserved
DataStartAddress[15:0]
reserved
Status2[2:0]
NrBytesToTransfer[14:0] (1 kB for full-speed)
S
Status1[2:0]
ISO_IN_0[7:0]
Type
ISO_IN_4[7:0]
[1:0]
EP
Token
[1:0]
Status0[2:0]
9
8
NrBytesTransferred[11:0]
DeviceAddress[6:0]
7
6
Frame[7:0] (full-speed)
5
ISO_IN_7[7:0]
ISO_IN_3[7:0]
SCS[7:0]
4
SA[7:0]
3
[2]
EndPt[3:1]
2
[1]
1
V
0

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