ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 95

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
ISP1760_4
Product data sheet
14.2.2 Single cycle: DMA write
Table 97.
T
Table 98.
T
Symbol
t
t
t
t
Symbol Parameter
V
t
t
t
t
t
t
t
t
V
t
t
t
t
t
t
t
t
w14
a34
a44
h14
a15
a25
h15
h25
su15
a35
cy15
w15
a15
a25
h15
h25
su15
a35
cy15
w15
amb
amb
Fig 20. DMA write (single cycle)
CC(I/O)
CC(I/O)
= 40 C to +85 C; unless otherwise specified.
= 40 C to +85 C; unless otherwise specified.
= 1.65 V to 1.95 V
= 3.3 V to 3.6 V
DREQ
WR_N
DREQ and DACK are active HIGH.
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
data hold time after WR_N de-assertion
DACK hold time after WR_N de-assertion
data set-up time before WR_N de-assertion
DREQ de-assertion time after WR_N assertion
last DACK strobe de-assertion to next DREQ
assertion time
WR_N pulse width
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
data hold time after WR_N de-assertion
DACK hold time after WR_N de-assertion
data set-up time before WR_N de-assertion
DREQ de-assertion time after WR_N assertion
last DACK strobe de-assertion to next DREQ
assertion time
WR_N pulse width
DACK
DATA
DMA read (single cycle)
DMA write (single cycle)
Parameter
RD_N pulse width
DREQ de-assertion time after RD_N assertion
DACK de-assertion to next DREQ assertion time -
data hold time after RD_N de-asserts
t
Rev. 04 — 4 February 2008
a25
t
a15
t
a35
t
w15
…continued
t
su15
data
t
h25
Embedded Hi-Speed USB host controller
t
cy15
t
h15
Min
> t
-
-
Min
0
1
3
0
5.5
-
-
22
0
1
2
0
5.5
-
-
22
d14
data 1
Max
-
18
56
5
Max
-
-
-
-
-
28
82
-
-
-
-
-
-
16
82
-
© NXP B.V. 2008. All rights reserved.
ISP1760
004aaa525
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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