NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 168
NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
Lead Free Status / RoHS Status
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Functional Description
5.14.10.1
Table 5-35. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)
168
Addr
00h
01h
02h
03h
04h
05h
06h
07h
08h
I/O
Rds
# of
2
2
2
2
2
2
2
2
6
Access
Write Only Registers with Read Paths in
ALT Access Mode
The registers described in
field in the table indicates which register will be returned per access to that port.
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
3
4
5
6
Restore Data
DMA Chan 0 base address low byte
DMA Chan 0 base address high byte
DMA Chan 0 base count low byte
DMA Chan 0 base count high byte
DMA Chan 1 base address low byte
DMA Chan 1 base address high byte
DMA Chan 1 base count low byte
DMA Chan 1 base count high byte
DMA Chan 2 base address low byte
DMA Chan 2 base address high byte
DMA Chan 2 base count low byte
DMA Chan 2 base count high byte
DMA Chan 3 base address low byte
DMA Chan 3 base address high byte
DMA Chan 3 base count low byte
DMA Chan 3 base count high byte
DMA Chan 0–3 Command
DMA Chan 0–3 Request
DMA Chan 0 Mode:
Bits(1:0) = 00
DMA Chan 1 Mode:
Bits(1:0) = 01
DMA Chan 2 Mode:
Bits(1:0) = 10
DMA Chan 3 Mode: Bits(1:0) = 11.
Data
Table 5-35
2
have read paths in ALT access mode. The access number
Addr
CAh
CCh
CEh
C4h
C6h
C8h
40h
41h
42h
70h
I/O
Intel
®
Rds
# of
I/O Controller Hub 6 (ICH6) Family Datasheet
7
1
1
1
2
2
2
2
2
2
Access
1
2
3
4
5
6
7
1
2
1
2
1
2
1
2
1
2
1
2
Restore Data
Timer Counter 0 status, bits [5:0]
Timer Counter 0 base count low byte
Timer Counter 0 base count high
byte
Timer Counter 1 base count high
byte
Timer Counter 2 base count low byte
Timer Counter 2 base count high
byte
Timer Counter 1 status, bits [5:0]
Timer Counter 2 status, bits [5:0]
Bit 7 = NMI Enable,
Bits [6:0] = RTC Address
DMA Chan 5 base address low byte
DMA Chan 5 base address high byte
DMA Chan 5 base count low byte
DMA Chan 5 base count high byte
DMA Chan 6 base address low byte
DMA Chan 6 base address high byte
DMA Chan 6 base count low byte
DMA Chan 6 base count high byte
DMA Chan 7 base address low byte
DMA Chan 7 base address high byte
DMA Chan 7 base count low byte
DMA Chan 7 base count high byte
Timer Counter 1 base count low byte
Data
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