NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 392
NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
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LPC Interface Bridge Registers (D31:F0)
10.7.4
10.7.5
392
COPROC_ERR—Coprocessor Error Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
RST_CNT—Reset Control Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bits
7:0
Bit
7:4
3
2
1
0
Coprocessor Error (COPROC_ERR) — WO. Any value written to this register will cause IGNNE#
to go active, if FERR# had generated an internal IRQ13. For FERR# to generate an internal IRQ13,
the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, Bit 13) must be 1.
Reserved
Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#, SLP_S4#,
and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PWROK going
low (with RSMRST# high), or after two TCO timeouts.
0 = ICH6 will keep SLP_S3#, SLP_S4# and SLP_S5# high.
1 = ICH6 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds.
NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion) in response
Reset CPU (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a hard or soft
reset, as determined by the SYS_RST bit (bit 1 of this register).
System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to the
processor.
0 = When RST_CPU bit goes from 0 to 1, the ICH6 performs a soft reset by activating INIT# for 16
1 = When RST_CPU bit goes from 0 to 1, the ICH6 performs a hard reset by activating PLTRST#
Reserved
PCI clocks.
and SUS_STAT# active for about 5-6 milliseconds, however the SLP_S3#, SLPS4# and
SLP_S5# will NOT go active. The ICH6 main power well is reset when this bit is 1. It also resets
the resume well bits (except for those noted throughout the Datasheet).
to SYSRESET#, PWROK#, and Watchdog timer reset sources.
F0h
00h
No
CF9h
00h
No
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Core
Core
WO
8-bits
R/W
8-bit
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