FDC37B782-NS Standard Microsystems (SMSC), FDC37B782-NS Datasheet

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FDC37B782-NS

Manufacturer Part Number
FDC37B782-NS
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of FDC37B782-NS

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Part Number:
FDC37B782-NS
Manufacturer:
MOT
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Part Number:
FDC37B782-NS
Manufacturer:
Microchip Technology
Quantity:
10 000
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5 Volt Operation
PC98/99 and ACPI 1.0 Compliant
Battery Back-up for Wake-Events
ISA Plug-and-Play Compatible Register Set
BIOS Buffer
20 GPI/O Pins
32KHz Standby Clock Output
Soft Power Management
ACPI/PME Support
SCI/SMI Support
Intelligent Auto Power Management
8042 Keyboard Controller
Real Time Clock
12 IRQ Options
15 Serial IRQ Options
16 Bit Address Qualification
Four DMA Options
12mA AT Bus Drivers
Watchdog timer
Power Button Override Event
Either Edge Triggered Interrupts
Shadowed Write-only Registers
Programmable Wake-up Event Interface
2K Program ROM
256 Bytes Data RAM
Asynchronous Access to Two Data
Registers and One Status Register
Supports Interrupt and Polling Access
8 Bit Timer/Counter
Port 92 Support
Fast Gate A20 and Hardware Keyboard
Reset
Day of Month Alarm, Century Byte
MC146818 and DS1287 Compatible
256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
Super I/O Controller with ACPI Support,
Real Time Clock and Consumer IR
FEATURES
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2.88MB Super I/O Floppy Disk Controller
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Enhanced FDC Digital Data Separator
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128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
12 and 24 Hour Time Format
Binary and BCD Format
5μA Standby Battery Current (max)
Relocatable to 480 Different Addresses
Licensed CMOS 765B Floppy Disk
Controller
Advanced Digital Data Separator
SMSC's Proprietary 82077AA
Compatible Core
Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power
Consumption
Supports Two Floppy Drives Directly
Software Write Protect
FDC on Parallel Port
Low Power CMOS Design
Supports Vertical Recording Format
16 Byte Data FIFO
100% IBM Compatibility
Detects All Overrun and Underrun
Conditions
24mA Drivers and Schmitt Trigger
Inputs
Low Cost Implementation
No Filter Components Required
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
Programmable Precompensation
Modes
FDC37B78x
1

Related parts for FDC37B782-NS

FDC37B782-NS Summary of contents

Page 1

... Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR 5 Volt Operation PC98/99 and ACPI 1.0 Compliant Battery Back-up for Wake-Events ISA Plug-and-Play Compatible Register Set 12 IRQ Options - 15 Serial IRQ Options - - 16 Bit Address Qualification - Four DMA Options - 12mA AT Bus Drivers ...

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Serial Ports - Relocatable to 480 Different Addresses Two High Speed NS16C550 Compatible - UARTs with Send/Receive 16 Byte - FIFOs Programmable Baud Rate Generator - Modem Control Circuitry Including 230K - and 460K Baud - IrDA 1.0, Consumer IR, ...

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FEATURES ........................................................................................................................................... 1 GENERAL DESCRIPTION ................................................................................................................. 6 DESCRIPTION OF PIN FUNCTIONS............................................................................................... 7 BUFFER TYPE DESCRIPTIONS .................................................................................................... 11 REFERENCE DOCUMENTS ........................................................................................................... 13 FUNCTIONAL DESCRIPTION......................................................................................................... 14 SUPER I/O REGISTERS ............................................................................................................... 14 HOST PROCESSOR INTERFACE .............................................................................................. 14 FLOPPY DISK CONTROLLER....................................................................................................... 16 FDC INTERNAL ...

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Description............................................................................................................................... 123 RUN STATE GPIO DATA REGISTER ACCESS................................................................ 123 GPIO OPERATION .................................................................................................................. 127 8042 KEYBOARD CONTROLLER DESCRIPTION ................................................................... 130 RTC INTERFACE............................................................................................................................. 138 SOFT POWER MANAGEMENT.................................................................................................... 148 ACPI/PME/SMI FEATURES........................................................................................................... 152 ACPI Features.......................................................................................................................... 152 Wake Events ............................................................................................................................. 153 PME SUPPORT........................................................................................................................ 154 ACPI/PME/SMI ...

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AC TIMING DIAGRAMS .............................................................................................................. 223 CAPACITIVE LOADING ......................................................................................................... 223 IOW Timing Port 92 ................................................................................................................ 224 POWER-UP TIMING................................................................................................................ 225 Button Timing.......................................................................................................................... 226 ROM INTERFACE.................................................................................................................... 227 ISA WRITE ................................................................................................................................ 228 ISA READ.................................................................................................................................. 229 8042 CPU .................................................................................................................................. 231 CLOCK TIMING........................................................................................................................ 232 Burst Transfer ...

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The FDC37B78x with advanced Consumer IR and IrDA v1.0 support incorporates a keyboard interface, real-time clock, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port which ...

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PD7 103 VSS 104 SLCT 105 PE 106 BUSY 107 nACK 108 nERROR 109 nALF 110 nSTROBE 111 RXD1 112 FDC37B78x TXD1 113 nDSR1 114 nRTS1/SYSOP 115 nCTS1 116 128 Pin QFP nDTR1 117 nRI1 118 nDCD1 119 nRI2 120 ...

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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME PROCESSOR/HOST INTERFACE (40) 44-47, System Data Bus 49-52 23-38 16-bit System Address Bus 43 Address Enable 64 I/O Channel Ready 53 ISA Reset Drive 40 Serial IRQ/IRQ15 39 PCI Clock/IRQ14/GP50 55 DMA Request ...

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PIN No./QFP NAME 7, 48, Digital Ground 74, 104 67 Analog Ground 69 Trickle Supply Voltage 65 Battery Voltage 19 Power On 20 Button In 21 Power Management Event/SCI/IRQ9 16 Read Disk Data 11 Write Gate 10 Write Disk Data ...

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PIN No./QFP NAME 79 General Purpose 12/WDT/P17/EETI 80 General Purpose 13/LED Driver 81 General Purpose 14/Infrared Rx 82 General Purpose 15/Infrared Tx (Note 3) 83 ROM Bus 0/IRQ1/GP60/nSMI 84 ROM Bus 1/IRQ3/GP61/LED 85 ROM Bus 2/IRQ4/GP62/nRING 86 ROM Bus 3/IRQ5/GP63/WDT ...

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PIN No./QFP NAME 127 Clear to Send 2 128 Data Terminal Ready 125 Data Set Ready 2 122 Data Carrier Detect 2 120 Ring Indicator 2 PARALLEL PORT INTERFACE (17) 96-103 Parallel Port Data Bus 95 Printer Select 94 Initiate ...

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BUFFER TYPE DESCRIPTIONS SYMBOL I Input, TTL compatible. IS Input with Schmitt trigger. ICLK RTC 32.768 kHz crystal input. OCLK RTC 32.768 kHz crystal output. IO4 Input/Output, 4mA sink, 2mA source. O4 Output, 4mA sink, 2mA source. O8 Output, 8mA ...

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PME#/SCI SOFT nPowerOn PME/ POWER ACPI Button_In MANAGEMENT POWER MANAGEMENT SER_IRQ SERIAL IRQ PCI_CLK ADDRESS BUS nIOR nIOW AEN SA[0:15] SD[O:7] HOST DRQ[0:3] CPU INTERFACE nDACK[0:3] TC IRQ[1,3-12,14] RESET_DRV IOCHRDY nINDEX nTRK0 nDSKCHG nWRPRT nWGATE Vtr Vss Vcc FIGURE 2 ...

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GENERAL PURPOSE I/O PINS TABLE 2 - GENERAL PURPOSE I/O PIN FUNCTIONS PIN NO. DEFAULT ALT QFP FUNCT FUNCT 1 77 GPIO nSMI 78 GPIO nRING 79 GPIO WDT 80 GPIO LED 81 GPIO IRRX2 82 GPIO IRTX2 4 nMTR1 ...

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FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS The address map, shown below in Table 4, shows the addresses of the different blocks of the Super I/O immediately after power up. addresses of the FDC, serial and parallel ports can be moved via ...

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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...

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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when ...

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PS/2 Model 30 Mode 7 INT DRQ PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active ...

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STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In ...

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PS/2 Model 30 Mode 7 6 nDRV2 nDS1 RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. (Always 1) BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. (Always 1) ...

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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR ...

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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE TAPE SEL1 (TDR. The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any ...

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TABLE 8 - INTERNAL 2 DRIVE DECODE - NORMAL DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit1 ...

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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...

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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration ...

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TABLE 11 - PRECOMPENSATION DELAYS PRECOMP 432 111 001 010 011 100 101 110 000 DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...

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TABLE 13 - DRVDEN MAPPING DT1 DT0 DRVDEN1 ( DRATE0 1 0 DRATE0 0 1 DRATE0 1 1 DRATE1 TABLE 14 - DEFAULT PRECOMPENSATION DELAYS DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps DRVDEN0 ...

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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time NON DMA RQM DIO ...

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CRC. Reads require the host to remove the remaining data so TABLE 15 - FIFO SERVICE DELAY FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 ...

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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 6 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in ...

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PS/2 Mode 7 6 DSK 1 CHG RESET N/A N/A COND. BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. ...

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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 14 for the settings corresponding to the individual data ...

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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 6 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table ...

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TABLE 16 - STATUS REGISTER 0 BIT NO. SYMBOL NAME 7,6 IC Interrupt Code 00 - Normal termination of command Seek End 4 EC Equipment Check Head Address The current head address. 1,0 DS1,0 Drive ...

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TABLE 17 - STATUS REGISTER 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writeable 0 MA Missing Address Mark DESCRIPTION The ...

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TABLE 18 - STATUS REGISTER 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...

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TABLE 19 - STATUS REGISTER 3 BIT NO. SYMBOL NAME Write Protected Track Head Address Indicates the status of the HDSEL pin. 1,0 DS1,0 Drive Select RESET There are three ...

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Model 30 mode - (IDENT low, MFM low) This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (FINTR and DRQ can active high and DENSEL ...

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This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, ...

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The generation of FINT determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must ...

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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...

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SYMBOL NAME HLT Head Load Time The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. HUT Head Unload Time The time interval from ...

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TABLE 21 - DESCRIPTION OF COMMAND SYMBOLS POLL Polling Disable When set, the internal polling routine is disabled. When clear, polling is enabled. PRETRK Precompensation Programmable from track 00 to FFH. Start Track Number R Sector Address The sector number ...

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INSTRUCTION SET PHASE R Command W MT MFM Execution Result TABLE 22 - INSTRUCTION SET READ DATA DATA BUS D5 D4 ...

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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...

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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...

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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...

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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...

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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...

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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...

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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W RECALIBRATE DATA BUS D5 ...

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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...

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PHASE R Command W 1 DIR PHASE R Command W 0 Execution Result ---- SRT ---- LOCK R 0 EIS EFIFO R RELATIVE SEEK ...

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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS ...

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PHASE R Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format ...

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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...

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The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. ...

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TABLE 25 - SKIP BIT VS READ DATA COMMAND DATA ADDRESS SK BIT MARK TYPE VALUE ENCOUNTERED SECTOR READ? 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data RESULTS CM BIT OF DESCRIPTION OF ST2 SET? RESULTS ...

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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. TABLE 26 - SKIP BIT VS. READ DELETED ...

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TABLE 27 - RESULT PHASE TABLE FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT ...

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EC bit to "0" and the EOT value equal to the final sector to be checked set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 27 ...

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SYSTEM 34 (DOUBLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 SYNC IDAM 80x 12x 50x 12x SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 SYNC IDAM 40x 6x 26x 6x FF ...

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TABLE 29 - TYPICAL VALUES FOR FORMATTING FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 5.25" 4096 ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 3.5" FM 256 512 Drives 256 MFM 512** 1024 GPL1 = ...

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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...

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Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the ...

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E 56 112 224 F 60 120 240 0 63.5 The choice of DMA or non-DMA operations is made by the ND bit. When this ...

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Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value returned as the result byte. Relative Seek The command is coded the same as for ...

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FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The ...

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D0-D3 are unaffected and retain their previous value. 2. "Hardware" resets will clear all bits TABLE 32 - EFFECTS OF WGATE AND GAP BITS WGATE GAP MODE 0 0 Conventional 0 1 Perpendicular (500 Kbps Reserved ...

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LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain ...

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Configuration section) define the base addresses of the serial ports. The Serial Port registers are located at sequentially increasing addresses above these base addresses. The chip TABLE 33 - ADDRESSING THE SERIAL PORT DLAB ...

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The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted ...

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Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 2 Setting this bit to ...

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TABLE 34 - INTERRUPT CONTROL FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY BIT 3 BIT 2 BIT 1 BIT 0 LEVEL Highest Second Second ...

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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...

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Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit ...

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Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start ...

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Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). indicates that the nRI input has changed ...

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Table 35 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock for 115.2k ; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k DESIRED DIVISOR USED TO BAUD RATE GENERATE 16X CLOCK 50 2304 ...

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Effect Of The Reset on Register File The Reset Function Table (TABLE 36) details the effect of the Reset input on each of the registers of the Serial Port. FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts ...

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FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, ...

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TABLE 36 - RESET FUNCTION REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) RESET/Read ...

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TABLE 37 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt ...

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TABLE 38 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL (CONTINUED) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status ...

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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...

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This filter circuit runs off of the 32 Khz clock. This circuit is ...

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The infrared interface provides a two-way wireless communications port using infrared transmission medium. Several IR implementations have been provided for the second UART in this chip (logical device 5), IrDA, Consumer Remote Control, and Amplitude Shift Keyed IR. The IR ...

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EPP DATA PORT 1 BASE ADDRESS + 05H EPP DATA PORT 2 BASE ADDRESS + 06H EPP DATA PORT 3 BASE ADDRESS + 07H D0 D1 DATA PORT PD0 PD1 STATUS PORT TMOUT 0 CONTROL STROBE AUTOFD PORT EPP ADDR ...

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TABLE 39 - PARALLEL PORT CONNECTOR HOST CONNECTOR PIN NUMBER 1 2 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the ...

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IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, ...

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BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 IRQE - INTERRUPT ...

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In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP ...

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The host selects an EPP register and drives nIOR active. 2. The chip drives IOCHRDY inactive (low WAIT is not asserted, the chip must wait until WAIT is asserted. 4. The chip tri-states the PData bus and ...

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Read Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri- states the PData bus. 2. The host selects an EPP register and drives nIOR active. 3. Chip ...

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TABLE 40 - EPP PIN DESCRIPTIONS EPP SIGNAL EPP NAME TYPE nWRITE nWrite O PD<0:7> Address/Data I/O INTR Interrupt I WAIT nWait I DATASTB nData Strobe O RESET nReset O ADDRSTB nAddress O Strobe PE Paper End I SLCT Printer ...

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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. • High performance half-duplex forward and reverse channel • Interlocked ...

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The bit map of the Extended Parallel Port registers is data PD7 PD6 ecpAFifo Addr/RLE dsr nBusy nAck dcr 0 0 Direction cFifo ecpDFifo tFifo cnfgA 0 0 cnfgB compress intrValue ecr MODE Note 1: These registers are ...

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TABLE 41 - ECP PIN DESCRIPTIONS NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...

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Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict ...

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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE ...

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BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer ...

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BITS [2:0] Parallel Port DMA (read-only) Refer to Table 44C. ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write and select the Mode. ...

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TABLE 44 - EXTENDED CONTROL REGISTER R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...

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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...

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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal ...

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After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert. An interrupt is generated when: 1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the ...

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DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more ...

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An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to <threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes ...

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NOTE : The Parallel Port Control register reads as “Cable Not Connected” when the Parallel Port FDC is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1. TABLE 47 - FDC PARALLEL PORT PINS SPP ...

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The Auto powerdown timer (10msec) must have timed out. An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when all the conditions are met. Disabling the auto powerdown ...

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TABLE 48 - PC/AT AND PS/2 AVAILABLE REGISTERS AVAILABLE REGISTERS BASE + ADDRESS PC-AT Access to these registers DOES NOT wake up the part 00H ---- 01H ---- 02H DOR (1) 03H --- 04H DSR (1) 06H --- 07H DIR ...

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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. TABLE 50 - STATE OF FLOPPY DISK DRIVE INTERFACE PINS IN POWERDOWN FDD PINS nRDATA ...

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UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter enters ...

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Internal PWRGOOD An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as V cycles on and off. cc When the internal PWRGOOD signal is “1” (active > 4V, and ...

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Timing Diagrams For IRQSER Cycle PCICLK = 33Mhz_IN pin IRQSER = SIRQ pin A) Start Frame timing with source sampled a low pulse on IRQ1 START FRAME PCICLK START IRQSER IRQ1 Host Controller Drive Source H=Host ...

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B) Stop Frame Timing with Host using 17 IRQSER sampling period IRQ14 IRQ15 FRAME FRAME PCICLK IRQSER None IRQ15 Driver 1) Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous ...

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IRQSER Data Frame Once a Start Frame has been initiated, the FDC37B78x will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and ...

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IRQSER PERIOD Note the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ number. The ...

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Stop Cycle Control Once all IRQ/Data Frames have completed the Host Controller will terminate IRQSER activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the IRQSER is low ...

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RD Bus Functionality The following cases described below illustrate the use of the RD Bus. Case 1: nROMCS and nROMOE as original function. The RD bus can be used as the RD bus or one or more RD pins can ...

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GENERAL PURPOSE I/O The FDC37B78x provides a set of flexible Input/Output control functions to the system designer through the 21 dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform simple I/O or can be individually configured ...

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Data port address is automatically set to the Index port address + 1. Upon exiting the configuration state the new Index TABLE 53 - INDEX AND DATA PORTS ...

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Each GPIO port has an 8-bit configuration register that controls the behavior of the pin. The GPIO configuration registers are only accessible when the FDC37B78x is in the Configuration state; more information can be found in the Configuration section of ...

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TABLE 55 - GPIO CONFIGURATION SUMMARY SELECTED DIRECTION FUNCTION BIT B0 GPIO ALT. X Note 1. For alternate function selects, the pin direction is set and controlled internally; i.e., regardless of ...

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GPIO OPERATION The operation of the GPIO ports is illustrated in FIGURE 3. Note: FIGURE 3 is for illustration purposes only and is not intended to suggest specific implementation details. D-TYPE SD-bit D Q GPx_nIOW Transparent Q D GPx_nIOR GPIO ...

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When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input ...

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KEYBOARD CONTROLLER DESCRIPTION A Universal Keyboard Controller designed for intelligent keyboard management in desktop computer applications is implemented. Universal Keyboard Controller uses an 8042 microcontroller CPU core. This 8042A P27 P10 P26 TST0 P23 TST1 P22 P11 Keyboard and ...

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KEYBOARD ISA INTERFACE The FDC37B78x ISA interface is functionally compatible with the 8042-style host interface. It consists of the D0-7 data bus; the nIOR, nIOW TABLE 57 - ISA I/O ADDRESS MAP ISA ADDRESS nIOW nIOR 0x60 0 1 0x64 ...

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Host-to-CPU Communication The host system can send both commands and data to the Input Data register. differentiates between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is "1", the CPU interprets ...

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However, as the oscillator cell will require an initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize. Program execution will resume as above. INTERRUPTS The FDC37B78x provides the two 8042 ...

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Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the FDC37B78x CPU. UD Writable by FDC37B78x CPU. These bits are user-definable. C/D (Command Data)-This bit specifies whether the input data ...

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GATEA20 AND KEYBOARD RESET The FDC37B78x provides two GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. Name Location Default Value Attribute Size Bit Function 7:6 Reserved. Returns 00 when read 5 ...

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P21 Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software ...

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P20 KRST_GA20 P92 Bit 0 Pulse Gen Note: When Port 92 is disabled, writes are ignored and reads return undefined values. Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low ...

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CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20 Gate A20 Turn-On Sequence Timing When writing to the command and data port with hardware speedup, the ...

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RTC INTERFACE The ISA interface is functionally compatible with the 8042-style host interface. It consists of the D0- 7 data bus, the nIOR, nIOW and the Status Table 61 - ISA I/O Address Map Addresses 0x60, 0x64, 0x70 and 0x71 ...

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Registers 00-0D are initialized to 00h. 2. Access to all registers from the host are blocked. RTC Interrupt The interrupt generated by the RTC is an active high output. The RTC interrupt output remains high as long as the ...

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Table 63 shows Bank 1, the second bank of CMOS registers which contains an additional 128 bytes of general purpose CMOS registers. Table 63 - Real Time Clock Address Map, Bank 1 ADDRESS REGISTER TYPE 0-7F R/W Note: CMOS Bank ...

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Table 64 - Time, Calendar and Alarm Bytes ADD REGISTER FUNCTION 0h Register 0: Seconds 1h Register 1: Seconds Alarm 2h Register 2: Minutes 3h Register 3: Minutes Alarm 4h Register 4: Hours (12 hour mode) (24 hour mode) 5h ...

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INPUT CLOCK FREQUENCY UIP BIT 32.768 kHz 32.768 kHz CONTROL AND STATUS REGISTERS, BANK 0 Bank 0 of the RTC has five registers that are accessible to the processor program at all times REGISTER A (AH) MSB ...

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Table 66 - Divider Selection Bits OSCILLATOR REGISTER A BITS FREQUENCY DV2 32.768 KHz 0 32.768 KHz 0 32.768 KHz 0 32.768 KHz 0 32.768 KHz 1 1 Table 67 - Periodic Interrupt Rates RATE SELECT RS3 RS2 RS1 RS0 ...

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PIE is not modified by any internal function, but is cleared to "0" RESET_DRV. AIE The alarm interrupt enable bit is a read/write bit, ...

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UF The update-ended interrupt flag bit is set after each update cycle. When the UIE bit is also a "1", the "1" causes the IRQF bit to be set and asserts IRQB. A RESET_DRV or a read of ...

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BIT 0 - AL_REM_EN One of the two control bits for the alarm wakeup function the “remember” enable bit for the second alarm. This bit, if set to 1, wil cause the system to power-up upon return of ...

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When the divider chain is changed from reset to the operating mode, the first ...

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SOFT POWER MANAGEMENT This chip employs soft power management to allow the chip to enter low power mode and to provide a variety of wakeup events to power up the chip. This technique allows for software control over powerdown and ...

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FIGURE 3 - SOFT POWER MANAGEMENT FUNCTIONAL DIAGRAM OFF_EN OFF_DLY Button L Button Input ED; PG SP1 ED; L EN1 nSPOFF1 SPx ED; L ENx nSPOFF1 PWRBTNOR_EN A transition on the Button input any enabled A low pulse ...

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REGISTERS The following registers can be accessed when in configuration mode at Logical Registers B0-B3, B8 and F4, and when not in configuration they can be accessed through the Index and Data Register. All soft power management configuration registers are ...

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It has a 0.5 second or faster resolution (run off of the 32kHz clock divided down) and the minimum time for triggering the override power down is four seconds, with a maximum of 4.5 seconds. ...

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ACPI/PME/SMI FEATURES ACPI Features The FDC37B78x supports ACPI as described in this section. These features comply with the ACPI Specification, Revision 1.0. Legacy/ACPI Select Capability This capability consists of an SMI/SCI switch which is required in a system that supports ...

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General Purpose ACPI Events The General Purpose ACPI events are enabled through the SCI_EN1 bit in the GPE_EN register. This bit, if set, allows any of the enabled PME events to generate an SCI. In addition, if the DEVINT_EN bit ...

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PME SUPPORT The FDC37B78x offers support for PCI power management events (PMEs). management event is requested by a PCI function via the assertion of the nPME signal. The assertion and deassertion of asynchronous to the PCI clock. FDC37B78x, active transitions ...

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The enable registers allow the setting of the status bit to generate an interrupt general rule ...

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Register Block The registers in this block are powered by VTR and battery backed up. TABLE 68 - PM1/GPE REGISTER BLOCK Register PM1_STS 1 PM1_STS 2 PM1_EN 1 PM1_EN 2 PM1_CNTRL 1 PM1_CNTRL 2 Reserved Reserved GPE_STS 1 GPE_EN 1 ...

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ACPI REGISTERS In the FDC37B78x, the PME wakeup events can be enabled as SCI events through the SCI_STS1 and SCI_EN1 bits in the GPE status and enable registers. See PME Interface and SMI/PME/SCI logic sections. Power Management 1 Status Register ...

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BIT NAME (Note 1) 4-6 Reserved Reserved. These bits always return a value of zero. 7 WAK_STS This bit is set when the system is in the sleeping state and an enabled wakeup event occurs. This bit is set on ...

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BIT NAME generate an SCI interrupt. When this bit is reset power management events will not generate an SCI interrupt. 1-7 Reserved Reserved. These bits always return a value of zero. Power Management 1 Control Register 2 (PM1_CNTRL 2) Register ...

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General Purpose Event Status Register 1 (GPE_STS1) Register Location: <PM1_BLK>+8 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT NAME 0 SCI_STS1 This bit is set when the device power management events (PME ...

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The PME_Status bit is read/write-clear. Writing a “1” to the PME_Status bit will clear it (if there are no pending PME events) and cause the FDC37C78X to stop asserting the nPME, if enabled. See Figure 5. • Writing a ...

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Size: 8-bits DEVINT_ RTC_PME nRING EN _EN PME Enable Register 2 (PME_EN2) Register Location: <PM1_BLK>+Fh System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits GP17 GP16 GP15 • ...

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SMI Status Register 1 (SMI_STS1) Register Location: <PM1_BLK>+12h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Status Register 1 This register is used to read the status of the SMI inputs. Default = ...

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SMI Enable Register 1 (SMI_EN1) Register Location: < PM1_BLK >+14h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Enable Register This register is used to enable the different interrupt sources onto the group ...

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SMI Enable Register 2 (SMI_EN2) Register Location: < PM1_BLK >+15h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Enable This register is used to enable the different interrupt sources onto the group Register ...

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EITHER EDGE TRIGGERED INTERRUPTS Four GPIO pins are implemented that allow an interrupt to be generated on both a high-to-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. The either edge ...

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FIGURE 5 - PME/SCI LOGIC MUX nPME nPME 0 0 nSCI pin 0 1 IRQ9 1 0 PME_STS Bit[6] Bits[6:5] Bit[5] of IRQ Mux Control Register PME_EN nSCI on IRQx pin GPE_EN Register nSCI SCI_EN1 GPE_EN.0 on Serial SCI_EN IRQx ...

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FIGURE 6 - SMI/PME LOGIC CONFIGURATION The Configuration of the FDC37B78x is very flexible and is based on the configuration Group architecture implemented in typical Plug-and-Play SMI components. The FDC37B78x is designed for nSMI motherboard applications in which the resources ...

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Entering the Configuration State The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = < 0x55> When in configuration mode, all logical devices function properly. Entering and configuration mode ...

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Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION MODE ;----------------------------' MOV DX,3F0H MOV AX,055H CLI ; disable interrupts OUT DX,AL STI ; enable interrupts ;-------------------------------. ; CONFIGURE REGISTER ...

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CONFIGURATION REGISTERS HARD INDEX TYPE RESET Vcc POR GLOBAL CONFIGURATION REGISTERS 0x02 W 0x00 0x03 R/W 0x03 0x07 R/W 0x00 0x20 R 0x44 0x21 R 0x00 (Note 0) 0x22 R/W 0x00 0x00 0x23 R/W 0x00 0x24 R/W 0x04 Sysopt=0: Sysopt=0: ...

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HARD INDEX TYPE RESET Vcc POR 0x30 R/W 0x00 0x60, R/W 0x00, 0x61 0x00 0x70 R/W 0x00 0x74 R/W 0x04 0xF0 R/W 0x3C 0xF1 R/W 0x00 LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1) 0x30 R/W 0x00 0x60, R/W 0x00, ...

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HARD INDEX TYPE RESET Vcc POR LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O) 0x30 R/W 0x00 0xB0 R/W - 0xB1 R/W - 0xB2 R 0xB3 R/W 0xB8 R/W - 0xC0 R/W - 0xC1 R/W 0x01 0xC2 R - ...

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HARD INDEX TYPE RESET Vcc POR 0xE5 R/W - 0xE6 R/W - 0xE7 R/W - 0xEF R/W - 0xF0 R/W - 0xF1 R/W 0x00 0xF2 R/W 0x00 0xF3 R/W 0x00 (1) 0xF4 R/W 0x00 0xF6 R/W - 0xF9 R/W - ...

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Chip Level (Global) Control/Configuration Registers [0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero ...

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REGISTER ADDRESS Device ID 0x20 R A identification. Bits[7:0] = 0x44 when read Hard wired = 0x44 Device Rev 0x21 R A read only register which provides device revision information. Bits[7:0] = 0x00 when read Hard wired = 0x00 PowerControl ...

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REGISTER ADDRESS Bit[7:1] Configuration Address Bits [7:1] Configuration 0x26 Bit[ Address Byte 0 See Note 1 Below Default=0xF0 (Sysopt=0) =0x70 (Sysopt=1) on Vcc POR or Reset_Drv Configuration 0x27 Bit[7:0] Configuration Address Bits [15:8] Address Byte 1 See Note ...

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Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports eight logical units and has eight sets of logical device registers. The eight logical devices are Floppy, Parallel Port, Serial ...

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LOGICAL DEVICE REGISTER ADDRESS (0x71,0x73) DMA Channel Select (0x74,0x75) Default = 0x04 on Vcc POR or Reset_Drv 32-Bit Memory (0x76-0xA8) Space Configuration Logical Device (0xA9-0xDF) Logical Device (0xE0-0xFE) Config. Reserved 0xFF Note 1: A logical device will be active and ...

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I/O Base Address Configuration Register TABLE 73 - I/O BASE ADDRESS CONFIGURATION REGISTER DESCRIPTION LOGICAL DEVICE LOGICAL REGISTER INDEX NUMBER DEVICE 0x00 FDC 0x60,0x61 (Note 4) 0x03 Parallel 0x60,0x61 Port 0x04 Serial Port 0x60,0x61 1 0x05 Serial Port 0x60,0x61 2 ...

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LOGICAL DEVICE LOGICAL REGISTER INDEX NUMBER DEVICE 0x62,0x63 0x06 RTC n/a 0x62, 0x63 0x07 KYBD n/a 0x0A ACPI 0x60,0x61 Note 3: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices. BASE ...

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Interrupt Select Configuration Register TABLE 74 - INTERRUPT SELECT CONFIGURATION REGISTER DESCRIPTION NAME REG INDEX Interrupt 0x70 (R/W) Bits[3:0] selects which interrupt level is used for Request Level Interrupt 0. Select 0 0x00=no interrupt selected. 0x01=IRQ1 0x02=IRQ2 Default = 0x00 ...

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DMA Channel Select Configuration Register TABLE 75 - DMA CHANNEL SELECT CONFIGURATION REGISTER DESCRIPTION NAME REG INDEX DMA Channel 0x74 (R/W) Select Default = 0x04 on Vcc POR or Reset_Drv Note: A DMA channel is activated by setting the DMA ...

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ECP Mode: i) (DMA) dmaEn from ecr register. See table. ii) IRQ - See table. MODE (FROM ECR REGISTER) 000 PRINTER 001 SPP 010 FIFO 011 ECP 100 EPP 101 RES 110 TEST 111 CONFIG 5) Real Time Clock ...

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These registers are not affected by soft resets. TABLE 76 - FLOPPY DISK CONTROLLER, LOGICAL DEVICE 0 [LOGICAL DEVICE NUMBER = 0X00] NAME REG INDEX FDD Mode 0xF0 R/W Bit[0] Floppy Mode Register = 0 Normal Floppy Mode (default) = ...

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NAME REG INDEX FDD0 0xF4 R/W Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Default = 0x00 Bits[4:3] Data Rate Table Select: DRT1, DRT0 Bits[5] on Vcc POR or Bits[6] Reset_Drv Bits[7] FDD1 0xF5 R/W Refer to definition and default for ...

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Parallel Port, Logical Device 3 TABLE 77 - PARALLEL PORT, LOGICAL DEVICE 3 [LOGICAL DEVICE NUMBER = 0X03] NAME REG INDEX PP Mode 0xF0 R/W Bits[2:0] Parallel Port Mode Register = 100 Printer Mode (default) = 000 Standard and Bi-directional ...

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Serial Port 1, Logical Device 4 TABLE 78 - SERIAL PORT 1, LOGICAL DEVICE 4 [LOGICAL DEVICE NUMBER = 0X04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv Note 1: ...

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TABLE 79 - UART INTERRUPT OPERATION UART1 UART1 UART1 UART2 OUT2 bit IRQ State OUT2 bit This part of the table is based on the assumption that both UARTS have selected different IRQ pins asserted 0 ...

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Serial Port 2, Logical Device 5 TABLE 80 - SERIAL PORT 2, LOGICAL DEVICE 5 [LOGICAL DEVICE NUMBER = 0X05] NAME REG INDEX Serial Port 2 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv IR Option ...

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RTC, Logical Device 6 TABLE 81 - RTC, LOGICAL DEVICE 6 [LOGICAL DEVICE NUMBER = 0X06] NAME REG INDEX RTC Mode Register 0xF0 R/W Default = 0x00 on Vcc POR or Reset_Drv Note 1: The secondary base address must be ...

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KYBD, Logical Device 7 TABLE 82 - KYBD, LOGICAL DEVICE 7 [LOGICAL DEVICE NUMBER = 0X07] NAME REG INDEX KRST_GA20 0xF0 R/W Default = 0x00 on Vcc POR or Reset_Drv 0xF1 - 0xFF DEFINITION KRESET and GateA20 Select Bit[7] Polarity ...

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Auxiliary I/O, Logical Device 8 TABLE 83 - AUXILLIARY I/O, LOGICAL DEVICE 8 [LOGICAL DEVICE NUMBER = 0X08] NAME REG INDEX Soft Power Enable 0xB0 R/W Register 1 Default = 0x00 on Vbat POR Soft Power Enable 0xB1 R/W Register ...

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NAME REG INDEX Soft Power Status 0xB2 R/W Register 1 Default = 0x00 on Vbat POR DEFINITION The following bits are the status for the wake-up function of the nPowerOn bit. These indicate which of the enabled wakeup functions caused ...

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NAME REG INDEX Soft Power Status 0xB3 R/W Register 2 Default = 0x00 on Vbat POR DEFINITION The following bits are the status for the wake-up function of the nPowerOn bit. These indicate which of the enabled wakeup functions caused ...

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NAME REG INDEX Delay 2 Time Set 0xB8 R/W Register Default = 0x00 on VTR POR DEFINITION This register is used to set Delay 2 (for Soft Power Management value from 500 msec to 32 sec. The default ...

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NAME REG INDEX IRQ Mux Control 0XC0 R/W Register Default = 0x00 on Vbat POR DEFINITION This register is used to configure the IRQs, including PME, SCI and SMI. Bit[0] Serial/Parallel IRQs 0=Serial IRQs are used 1=Parallel IRQS are used ...

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NAME REG INDEX Forced Disk Change 0xC1 R/W Default = 0x03 on VTR POR Floppy Data Rate 0xC2 R Select Shadow UART1 FIFO 0xC3 R Control Shadow UART2 FIFO 0xC4 R Control Shadow DEFINITION Force Change 1 and Force Change ...

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NAME REG INDEX Forced Write Protect 0xC5 R/W Default = 0x00 on VTR POR Ring Filter Select 0xC6 R/W Register Default = 0x00 on Vbat POR Note 3 Note 1: There are three types of events Type 1, Type 2 ...

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Note 2: nWRTPRT (to the FDC Core) = (nDS0 AND FORCE WRTPRT 0) OR nWRTPRT (from the FDD Interface). The Force Write Protect 0 bit also applies to the Parallel Port FDC. This bit applies to both drives. Note 3: ...

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TABLE 84 - AUXILLIARY I/O, LOGICAL DEVICE 8 [LOGICAL DEVICE NUMBER = 0X08] NAME REG INDEX GP10 0xE0 General Purpose I/0 bit 1.0 Bit[0] In/Out : =1 Input, =0 Output Default = 0x01 Bit[1] Polarity : =1 Invert ...

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NAME REG INDEX Default = 0x01 Bit[1] Polarity : =1 Invert Invert on Vbat POR Bit[2] Group Interrupt Enable =1 Enable Combined IRQ 1 =0 Disable Combined IRQ 1 Bit[3] Function Select =1 LED =0 GPI/O Bits[6:4] Reserved ...

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