FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 193
FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
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5.19.1.2
Intel
®
Figure 20. Transfer Descriptor
Table 82. TD Link Pointer
82801EB ICH5 / 82801ER ICH5R Datasheet
Transfer Descriptor (TD)
Transfer Descriptors (TDs) express the characteristics of the transaction requested on USB by a
client. TDs are always aligned on 16-byte boundaries, and the elements of the TD are shown in
Figure
the descriptor that the ICH5 interprets during operation. All TDs have the same, basic, 32-byte
structure. During operation, the ICH5 hardware performs consistency checks on some fields of the
TD. If a consistency check fails, the ICH5 halts immediately and issues an interrupt to the system.
This interrupt cannot be masked within the ICH5.
R = Reserved
Bits
31:4
31
3
2
1
0
R
Intel
30
20. The four, different USB transfer types are supported by a small number of control bits in
®
SPD
ICH5 Read/Write
29
Link Pointer (LP). Bits [31:4] correspond to memory address signals [31:4], respectively. This
field points to another TD or QH.
Reserved. Must be 0 when writing this field.
Depth/Breadth Select (VF). This bit is only valid for queued TDs and indicates to the hardware
whether it should process in a depth first or breadth first fashion. When set to depth first, it informs
the ICH5 to process the next transaction in the queue rather than starting a new queue.
0 = Breadth first
1 = Depth first
QH/TD Select (Q). This bit informs the Intel
is another TD or a QH. This allows the ICH5 to perform the proper type of processing on the item
after it is fetched.
0 = TD
1 = QH
Terminate (T). This bit informs the ICH5 that the link pointer in this TD does not point to another
valid entry. When encountered in a queue context, this bit indicates to the ICH5 that there are no
more valid entries in the queue. A TD encountered outside of a queue context with the T bit set
informs the ICH5 that this is the last TD in the frame.
0 = Link Pointer field is valid.
1 = Link Pointer field not valid.
28
C_ERR LS
MaxLen
27
26
ISO ISC
25
24
23
ICH5 Read Only
21
Link Pointer
20
Status
R
19
D
Buffer Pointer
18
EndPt
Description
16
®
ICH5 whether the item referenced by the link pointer
15
14
R
Device Address
11
10
Functional Description
8
7
ActLen
PID
4
3
0
Vf
2
1
Q
0
T
193
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