FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 494
FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
Lead Free Status / RoHS Status
Not Compliant
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EHCI Controller Registers (D29:F7)
494
15:14
13:6
Bit
19
18
17
16
5
4
3
2
1
0
SMI on Periodic — R/WC. Software clears this bit by writing a 1 it.
0 = No Periodic Schedule Enable bit change.
1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1.
SMI on CF — R/WC. Software clears this bit by writing a 1 it.
0 = No Configure Flag (CF) change.
1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1.
SMI on HCHalted — R/WC. Software clears this bit by writing a 1 it.
0 = HCHalted did not transition to 1 (as a result of the Run/Stop bit being cleared).
1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared).
SMI on HCReset — R/WC. Software clears this bit by writing a 1 it.
0 = HCRESET did not transitioned to 1.
1 = HCRESET transitioned to 1.
Reserved — RO. Hardwired to 00h
SMI on PortOwner Enable — R/W.
0 = Disable
1 = Enable. When any of these bits are 1 and the corresponding SMI on PortOwner bits are 1, then
SMI on PMSCR Enable — R/W.
0 = Disable
1 = Enable. When this bit is 1 and SMI on PMSCR is 1, then the host controller will issue an SMI.
SMI on Async Enable — R/W.
0 = Disable
1 = Enable. When this bit is 1 and SMI on Async is 1, then the host controller will issue an SMI
SMI on Periodic Enable — R/W.
0 = Disable
1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller will issue an SMI.
SMI on CF Enable — R/W.
0 = Disable
1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will issue an SMI.
SMI on HCHalted Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host controller will issue an
SMI on HCReset Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller will issue an SMI—
the host controller will issue an SMI. Unused ports should have their corresponding bits
cleared.
SMI.
R/W.
Intel
Description
®
82801EB ICH5 / 82801ER ICH5R Datasheet
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