CY7C63723-SCT Cypress Semiconductor Corp, CY7C63723-SCT Datasheet

CY7C63723-SCT

Manufacturer Part Number
CY7C63723-SCT
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C63723-SCT

Lead Free Status / RoHS Status
Not Compliant
Features
Cypress Semiconductor Corporation
Document #: 38-08022 Rev. *D
enCoRe™ USB - enhanced Component Reduction
Flexible, cost-effective solution for applications that combine
PS/2 and low-speed USB, such as mice, gamepads, joysticks,
and many others.
USB Specification Compliance
8-bit RISC microcontroller
I/O ports
Internal oscillator eliminates the need for an external crystal
or resonator
Interface can auto-configure to operate as PS/2 or USB with-
out the need for external components to switch between
modes (no General Purpose I/O [GPIO] pins needed to man-
age dual mode capability)
Internal 3.3V regulator for USB pull-up resistor
Configurable GPIO for real-world interface without external
components
Conforms to USB Specification, Version 2.0
Conforms to USB HID Specification, Version 1.1
Supports one low-speed USB device address and three data
endpoints
Integrated USB transceiver
3.3V regulated output for USB pull-up resistor
Harvard architecture
6-MHz external ceramic resonator or internal clock mode
12-MHz internal CPU clock
Internal memory
256 bytes of RAM
8 Kbytes of EPROM
Interface can auto-configure to operate as PS/2 or USB
No external components for switching between PS/2 and
USB modes
No GPIO pins needed to manage dual mode capability
Up to 16 versatile GPIO pins, individually configurable
High current drive on any GPIO pin: 50 mA/pin current sink
Each GPIO pin supports high-impedance inputs, internal
pull-ups, open drain outputs or traditional CMOS outputs
Maskable interrupts on all I/O pins
198 Champion Court
enCoRe™ USB Combination Low-Speed
USB and PS/2 Peripheral Controller
SPI serial communication block
Four 8-bit Input Capture registers
Internal low-power wake-up timer during suspend mode
Optional 6-MHz internal oscillator mode
Watchdog Reset (WDR)
Low-voltage Reset at 3.75V
Internal brown-out reset for suspend mode
Improved output drivers to reduce EMI
Operating voltage from 4.0V to 5.5VDC
Operating temperature from 0°C to 70°C
CY7C63723C available in 18-pin SOIC, 18-pin PDIP
CY7C63743C available in 24-pin SOIC, 24-pin PDIP, 24-pin
QSOP
CY7C63722C available in DIE form
Industry standard programmer support
Master or slave operation
2 Mbit/s transfers
Two registers each for two input pins
Capture timer setting with five prescaler settings
Separate registers for rising and falling edge capture
Simplifies interface to RF inputs for wireless applications
Periodic wake-up with no external components
Allows fast start-up from suspend mode
San Jose
,
CA 95134-1709
Revised October 20, 2010
CY7C63722C
CY7C63723C
CY7C63743C
408-943-2600
[+] Feedback

Related parts for CY7C63723-SCT

CY7C63723-SCT Summary of contents

Page 1

... Improved output drivers to reduce EMI ■ Operating voltage from 4.0V to 5.5VDC ■ Operating temperature from 0°C to 70°C ■ CY7C63723C available in 18-pin SOIC, 18-pin PDIP ■ CY7C63743C available in 24-pin SOIC, 24-pin PDIP, 24-pin ■ QSOP CY7C63722C available in DIE form ■ ...

Page 2

... The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 μs and 1.024 ms). The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an CY7C63722C CY7C63723C CY7C63743C Capture SPI Timers ...

Page 3

... P0.5 P0.6 P0 P0.7 P0 P1.1 P1 VSS D+/SCLK 12 VPP 7 D–/SDATA 11 VREG/P2.0 8 VCC 10 9 XTALIN/P2.1 XTALOUT Pin Definitions CY7C63723C CY7C63743C CY7C63722C Name I/O 18-Pin D–/SDATA, I/O 12 D+/SCLK 13 P0[7:0] I 15, 16, 17, 18 21, 22, 23, 24 P1[7:0] I 17, 18, 19, 20 XTALIN/P2 XTALOUT OUT VREG/P2.0 8 ...

Page 4

... The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above. DSPINIT: EQU 30h ■ CY7C63722C CY7C63723C CY7C63743C Page [+] Feedback ...

Page 5

... PUSH A 6 PUSH X 7 SWAP A,X 4 SWAP A,DSP 6 MOV [expr],A direct 7 MOV [X+expr],A index 4 OR [expr],A direct 6 OR [X+expr],A index 7 AND [expr],A direct 5 AND [X+expr],A index 7 XOR [expr],A direct 8 XOR [X+expr],A index 4 IOWX [X+expr] index CY7C63722C CY7C63723C CY7C63743C Operand Opcode Cycles ...

Page 6

... JZ addr A0-AF JNZ addr B0-BF Document #: 38-08022 Rev. *D Cycles MNEMONIC 5 CPL 6 ASL 4 ASR 5 RLC RRC 4 RET RETI addr 10 JNC addr 5 (or 4) JACC addr 5 (or 4) INDEX addr CY7C63722C CY7C63723C CY7C63743C Operand Opcode Cycles C0-CF 5 (or 4) D0-DF 5 (or 4) E0-EF 7 F0-FF 14 Page [+] Feedback ...

Page 7

... SPI interrupt vector 0x0010 Capture timer A interrupt Vector 0x0012 Capture timer B interrupt vector 0x0014 GPIO interrupt vector 0x0016 Wake-up interrupt vector 0x0018 Program Memory begins here 0x1FDF 8 KB PROM ends here ( bytes). See Note below CY7C63722C CY7C63723C CY7C63743C Page [+] Feedback ...

Page 8

... Interrupt enable for pins in Port 0 W Interrupt enable for pins in Port 1 W Interrupt polarity for pins in Port 0 W Interrupt polarity for pins in Port 1 W Controls output configuration for Port Controls output configuration for Port 1 W CY7C63722C CY7C63723C CY7C63743C (Figure 33). All Function Fig ...

Page 9

... Falling edge Capture Timer B data register R/W Capture Timer configuration register R Capture Timer status register R/W SPI read and write data register R/W SPI status and control register R/W Internal / External Clock configuration register R/W Processor status and control CY7C63722C CY7C63723C CY7C63743C Fig ...

Page 10

... Wake-up Timer Adjust Bit [2:0], as described in Section . One common use of the wake-up interrupts is to generate periodical wake-up events during suspend mode to check for changes, such as looking for movement in a mouse, while maintaining a low average power. CY7C63722C CY7C63723C CY7C63743C XTALOUT XTALIN ...

Page 11

... Low-voltage Reset (LVR) 2. Brown Out Reset (BOR) 3. Watchdog Reset (WDR) The occurrence of a reset is recorded in the Processor Status and Control Register (Figure 33). Bits 4 (Low-voltage or CY7C63722C CY7C63723C CY7C63743C ; Set Bit 0 HIGH (External Oscillator Enable bit). Bit 7 cleared gives faster start-up ; Write to Clock Configuration ...

Page 12

... Section for more details). A Watchdog ). During this t START Timer Reset typically lasts for 2–4 ms, after which the microcon- troller begins execution at ROM address 0x0000 MHz) 2–4 ms WDR goes HIGH for 2–4 ms CY7C63722C CY7C63723C CY7C63743C pin voltage drops below V CC LVR drops CC voltage to the CC drops and ...

Page 13

... This can be done by timing the wake-up interrupt time with the accurate 1.024-ms timer interrupt, and adjusting the Timer Adjust bits accordingly to approximate the desired wake-up time. CY7C63722C CY7C63723C CY7C63743C Page [+] Feedback ...

Page 14

... Interrupt Enable Port 8-bit port; Port 1 contains either 2 bits, P1.1–P1.0 in the CY7C63723C, or all 8 bits, P1.7–P1.0 in the CY7C63743C parts. Each bit can also be selected as an interrupt source for the microcontroller, as explained in Section . The data for each GPIO pin is accessible through the Port Data register ...

Page 15

... Low Sink Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data ■ Register = 0) Q1 and Q3 are OFF ON. The GPIO pin is capable sinking current. Medium Sink Mode (Mode1 = 0, Mode0 = 1, and the pin’s Data ■ Register = and Q3 are OFF ON. The GPIO pin is capable of sinking current. CY7C63722C CY7C63723C CY7C63743C P1[7:0] Mode0 ...

Page 16

... P2.1 P2.0 (Internal VREG Coordinate enumeration by decoding USB device requests. ■ Clock Pin Fill and empty the FIFOs. ■ Mode State Only) Suspend/Resume coordination. ■ Verify and select Data toggle values. ■ CY7C63722C CY7C63723C CY7C63743C Page [+] Feedback ...

Page 17

... D– pins in USB mode, D+/D– Forcing Bit 2 should be 0. Set- ting D+/D– Forcing Bit 2 to ‘1’ puts both pins in an open-drain mode, preferred for applications such as PS/2 or LED driving. CY7C63722C CY7C63723C CY7C63743C if the VREG Enable bit is REG with two resistors of approxi ...

Page 18

... Bit 6: IN Received valid IN packet has been received. This bit is updated to ‘1’ after the last received packet transaction. This bit is cleared by any non-locked writes to the register received. This bit is cleared by any non-locked writes to the register. CY7C63722C CY7C63723C CY7C63743C 3:0 IN OUT ...

Page 19

... CRC, bitstuff, or PID errors have occurred. This bit does not update for some endpoint mode settings. Refer to Table 10 for more details Data is valid Data is invalid. If enabled, the endpoint interrupt will occur even if invalid data is received. CY7C63722C CY7C63723C CY7C63743C Data Data ...

Page 20

... Bits [2:0] of the USB Status and Control Register. 6. The V pin can be placed into a high-impedance state, so REG that a USB pull-up resistor on the D–/SDATA pin will not OH interfere with PS/2 operation (bit 6, USB Status and Control Register). The PS/2 on-chip support circuitry is illustrated in CY7C63722C CY7C63723C CY7C63743C . CC Figure 19. Page [+] Feedback ...

Page 21

... Figure 19. Diagram of USB-PS/2 System Connections Port 2.0 VREG Enable Port 2.5 Document #: 38-08022 Rev. *D 200Ω 3.3V Regulator V CC PS/2 Pull-up Enable 5 kΩ 5 kΩ USB - PS/2 Driver Port 2.4 On-chip CY7C63722C CY7C63723C CY7C63743C VREG 1.3 kΩ D+/SCLK D–/SDATA Off-chip Page [+] Feedback ...

Page 22

... MISO pin (P0.6). The output pins must be set to the desired drive strength, and the GPIO data register must be set enable a bypass mode for these pins. The MISO pin must be configured in the desired GPIO input mode. See Section for GPIO configuration details. CY7C63722C CY7C63723C CY7C63743C MOSI Master / Slave MISO ...

Page 23

... SCK idles HIGH SCK idles LOW. Bit 2: CPHA SPI Clock Phase bit (see Bit [1:0]: SCK Select Master mode SCK frequency selection (no effect in Slave Mode Mbit Mbit 0.5 Mbit 0.0625 Mbit/s CY7C63722C CY7C63723C CY7C63743C Figure 22. The timing Comm CPOL CPHA SCK ...

Page 24

... For Slave Mode active LOW input. P0.5 Data output for master, data input for slave. P0.6 Data input for master, data output for slave. P0.7 SPI Clock: Output for master, input for slave. CY7C63722C CY7C63723C CY7C63743C LSB x LSB Comment Page [+] Feedback ...

Page 25

... Bit [7:0]: Timer lower eight bits Figure 25. Timer MSB Register (Address 0x25) Bit # Bit Name Read/Write Reset Bit [7:4]: Reserved Bit [3:0]: Timer upper four bits Figure 26. Timer Block Diagram CY7C63722C CY7C63723C CY7C63743C Reserved Timer [11: 1.024-ms interrupt 128- μ s interrupt 0 1 MHz clock D0 To Timer Registers ...

Page 26

... Figure 27. Capture Timers Block Diagram Prescaler Mux 8-bit Capture Registers Timer A Rising Edge Time Timer A Falling Edge Time Timer B Rising Edge Time Timer B Falling Edge Time CY7C63722C CY7C63723C CY7C63743C Figure . 1 MHz Clock Capture Timer A Interrupt Request Capture Timer B Interrupt Request Page [+] Feedback ...

Page 27

... This is also true for Capture B events Figure 32. Capture Timer Configuration Register (Address 0x44 Bit # Bit First Name Edge Hold Read/ R/W R/W R/W R Write Reset CY7C63722C CY7C63723C CY7C63743C Capture Capture Capture Capture Falling Rising Falling Rising Event Event Event Event - - - ...

Page 28

... Bits 7:0 of free-running timer Table 6 below. 001 Bits 8:1 of free-running timer 010 Bits 9:2 of free-running timer 011 Bits 10:3 of free-running timer 100 Bits 11:4 of free-running timer CY7C63722C CY7C63723C CY7C63743C = 6 MHz) LSB Captured Bits Step Range Size 1 μs 256 μs 2 μs 512 μs 4 μ ...

Page 29

... This bit is manipulated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at the end of the current instruction. The processor remains halted until a reset occurs (low-voltage, brown-out, or Watchdog). This bit should normally be written as a ‘1’. CY7C63722C CY7C63723C CY7C63743C Interrupt ...

Page 30

... Interrupt Service Routine will execute a minimum of 16 clocks (1+10+ maximum of 20 clocks (5+10+5) after the interrupt is issued. With a 6-MHz external resonator, internal CPU clock speed is 12 MHz clocks take 20/12 MHz = 1.67 μs. CY7C63722C CY7C63723C CY7C63743C Page [+] Feedback ...

Page 31

... Enable. Periodic interrupts will be generated approximate- ly every 128 μ Disable. CY7C63722C CY7C63723C CY7C63743C 1.024-ms 128-μs ...

Page 32

... USB host during the host attempts to read data from 0 0 the endpoint (INs). The device SIE sends a NAK or STALL handshake packet ❐ to the USB host during the host attempts to write data (OUTs) to the endpoint FIFO Enable EP0 interrupt 0 = Disable EP0 interrupt CY7C63722C CY7C63723C CY7C63743C for more information. Page [+] Feedback ...

Page 33

... Reset 0 Figure 39. Port 0 Interrupt Polarity Register (Address 0x06 Bit [7:0]: P0[7:0] Interrupt Polarity 1 = Rising GPIO edge 0 = Falling GPIO edge CY7C63722C CY7C63723C CY7C63743C To CPU CPU IRQ Pending (Bit 7, Reg 0xFF) IRQ Global Int Enable Interrupt Sense Enable (Bit 2, Reg 0xFF) Bit Controlled by DI, EI, and ...

Page 34

... Bit [7:0]: P1[7:0] Interrupt Polarity 1 = Rising GPIO edge 0 = Falling GPIO edge Figure 41. GPIO Interrupt Diagram GPIO Interrupt OR Gate Flip Flop (1 input per GPIO pin CLR Global 1 = Enable GPIO Interrupt 0 = Disable Enable (Bit 6, Register 0x20) CY7C63722C CY7C63723C CY7C63743C IRQout Interrupt Priority Interrupt Encoder Vector Page [+] Feedback ...

Page 35

... Some Mode Bits are automatically changed by the SIE in response to many USB transactions. For example, if the Mode Bits [3:0] are set to '1111' which is ACK IN-Status OUT mode as shown in Table 8, the SIE will change the endpoint Mode Bits CY7C63722C CY7C63723C CY7C63743C Page [+] Feedback ...

Page 36

... COUNT Setup In Out Bit[3:0], Figure 18 Data Valid (Bit 6, Figure 18) Data 0/1 (Bit 7, Figure 18) PID Status Bits (Bit[7:5], Figure 16) TX: transmit TX0: transmit 0-length packet RX: receive CY7C63722C CY7C63723C CY7C63743C Interrupt? End Point Mode Re- ACK sponse Int SIE’s Re- sponse Endpoint Mode changed by the SIE ...

Page 37

... up- up- U dates 1 dates up- up- up- U dates dates dates up- up- U dates 0 dates CY7C63722C CY7C63723C CY7C63743C Set End Point Mode ACK Response Int ACK s NoChang Ignore s NoChang Ignore s NoChang UC e Ignore no NoChang NAK s NoChang UC e Ignore no NoChang UC e Ignore no NoChang NAK s NoChang UC e Ignore ...

Page 38

... U dates 1 dates up dates up dates up- up- U dates 1 dates CY7C63722C CY7C63723C CY7C63743C NoChang NAK s NoChang NAK s NoChang UC e Ignore no NoChang UC e Ignore no NoChang Byte STALL s NoChang UC e Ignore no NoChang UC e Ignore no NoChang Byte s NoChang ACK STALL STALL s NoChang UC e Ignore no NoChang UC e Ignore ...

Page 39

... C UC up- up- up- U dates dates dates CY7C63722C CY7C63723C CY7C63743C ACK s NoChang Ignore s NoChang Ignore s NoChang UC e Ignore no NoChang STALL s NoChang UC e Ignore no NoChang UC e Ignore no NoChang UC e Ignore no NoChang NAK s NoChang UC e Ignore no NoChang UC e Ignore no NoChang UC e Ignore no NoChang NoChang ...

Page 40

... Enable Reserved Capture B Capture B Falling Rising Event Event Watch Dog Bus LVR/BOR Suspend Interrupt Reset Interrupt Reset Enable Event Sense CY7C63722C CY7C63723C CY7C63743C Read/Write/ Default/ Bit 1 Bit 0 Both/ Reset 00000000 BBBBBBBB 00000000 BBBBBBBB P2.1 (Int Clk VREG Pin -- -- 00000000 RR RR Mode Only ...

Page 41

... Cumulative across all ports V below V for >100 ns CC LVR [8] linear ramp [9, 10] Load = External cap not required [ Gnd suspend or with LVR disabled, BOR occurs whenever V LVR is connected from D– to ground. PD CY7C63722C CY7C63723C CY7C63743C Min. Max. Unit V 5.5 V LVR 4.35 5. μA 25 μA 75 –0.4 0.4 V μ ...

Page 42

... High to low edge, Port High to low edge, Port Ports 0, 1, and 2 [ mA, Ports OL1 [ mA, Ports OL1 [ mA, Ports OL2 [ mA, Ports OL3 [4] Port Internal Clock Mode only CY7C63722C CY7C63723C CY7C63743C Min. Max. Unit 0.3 V 2.7 3.6 V 0.2 V 0.8 2.5 V 0.8 2 μA –10 10 1.274 1.326 kΩ ...

Page 43

... To Next Transition [15] For Paired Transitions [15] Accepts as EOP To next transition, Figure 46 To paired transition, Figure 46 Note 16 CLoad = 150 pF to 600 pF [17] See Figures /3; see Figure 20 CLK CY7C63722C CY7C63723C CY7C63743C Min. Max. Unit 5.7 6.3 MHz 5.91 6.09 MHz 164.2 169 CYC ...

Page 44

... Time before leading SCK edge SCK to data valid Time after SS LOW to data valid Before first SCK edge After last SCK edge Figure 42. Clock Timing T CYC Figure 43. USB Data Signal Timing 90% 90% 10% 10% CY7C63722C CY7C63723C CY7C63743C Min. Max. Unit 125 ns 125 ns – 100 ...

Page 45

... PERIOD JR2 Crossover Point Extended Point Diff. Data to SE0 Skew + T PERIOD DEOP Figure 46. Differential Data Jitter Crossover Points Consecutive Transitions PERIOD xJR1 Paired Transitions PERIOD xJR2 CY7C63722C CY7C63723C CY7C63743C T JR2 Source EOP Width: T EOPT Receiver EOP Width EOPR1 EOPR2 Page [+] Feedback ...

Page 46

... T T SSU SDO MISO Document #: 38-08022 Rev. *D Figure 47. SPI Master Timing, CPHA = 0 (SS is under firmware control in SPI Master mode) T SCKL MSB T MHD Figure 48. SPI Slave Timing, CPHA = 0 T SCKL T SHD MSB CY7C63722C CY7C63723C CY7C63743C LSB LSB T SSH LSB LSB Page [+] Feedback ...

Page 47

... T T SSU SHD T SDO1 MISO MSB Document #: 38-08022 Rev. *D Figure 49. SPI Master Timing, CPHA = 1 (SS is under firmware control in SPI Master mode) T SCKL T MDO Figure 50. SPI Slave Timing, CPHA = 1 T SCKL T SDO CY7C63722C CY7C63723C CY7C63743C LSB LSB T SSH LSB LSB Page [+] Feedback ...

Page 48

... Small Outline Lead-free Package P13 24-Pin (300-Mil) Lead-free PDIP S13 24-Pin Small Outline Lead-free Package Q13 24-lead QSOP Lead-free Package – 25-Pad DIE Form Figure 51. 18-Pin PDIP (300-Mil) Molded DIP CY7C63722C CY7C63723C CY7C63743C Operating Range Commercial Commercial Commercial Commercial Commercial Commercial 51-85010 *C ...

Page 49

... Figure 53. 24-Pin SOIC (.615 X .300 X .0932 Inches Document #: 38-08022 Rev. *D Figure 52. 18L SOIC .463 X.300 X .0932 Inches CY7C63722C CY7C63723C CY7C63743C 51-85023 *C 51-85025 *D Page [+] Feedback ...

Page 50

... Document #: 38-08022 Rev. *D Figure 54. 24-Pin PDIP 1.260 X .270 X .140 I Figure 55. 24-Pin QSOP 8.65 X 3.9 X 1.44 MM CY7C63722C CY7C63723C CY7C63743C 51-85013 *C 51-85055 *C Page [+] Feedback ...

Page 51

... D– 1662.35 D+ 1735.35 P1.7 1752.05 P1.5 1752.05 P1.3 1752.05 P1.1 1752.05 P0.7 1752.05 P0.6 1393.25 P0.5 1171.80 P0.4 980.35 CY7C63722C CY7C63723C CY7C63743C Y (microns) 2843.15 2843.15 2843.15 2687.95 2496.45 2305.05 2113.60 1922.05 1730.90 312.50 184.85 184.85 184.85 184.85 184.85 184.85 289.85 1832.75 2024 ...

Page 52

... Document History Page Document Title: CY7C63722C, CY7C63723C, CY7C63743C enCoRe™ USB Combination Low-Speed USB and PS/2 Peripheral Controller Document Number: 38-08022 Orig. of REV. ECN NO. Issue Date Change ** 118643 10/22/02 BON *A 243308 SEE ECN KKU *B 267229 See ECN ARI *C 429169 See ECN ...

Page 53

... Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-08022 Rev. *D enCoRe is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised October 20, 2010 CY7C63722C CY7C63723C CY7C63743C PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...

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