FW82801EB Intel, FW82801EB Datasheet - Page 112

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.5.5
5.5.5.1
5.5.5.2
5.5.5.3
112
Software Commands
There are three additional special software commands that the DMA controller can execute. The
three software commands are:
They do not depend on any specific bit pattern on the data bus.
Clear Byte Pointer Flip-Flop
This command is executed prior to writing or reading new address or word count information to/
from the DMA controller. This initializes the flip-flop to a known state so that subsequent accesses
to register contents by the microprocessor will address upper and lower bytes in the correct
sequence.
When the host processor is reading or writing DMA registers, two Byte Pointer flip-flops are used;
one for channels 0–3 and one for channels 4–7. Both of these act independently. There are separate
software commands for clearing each of them (0Ch for channels 0–3, 0D8h for channels 4–7).
DMA Master Clear
This software instruction has the same effect as the hardware reset. The Command, Status,
Request, and Internal First/Last Flip-Flop registers are cleared and the Mask register is set. The
DMA controller enters the idle cycle.
There are two independent master clear commands; 0Dh that acts on channels 0–3, and 0DAh that
acts on channels 4–7.
Clear Mask Register
This command clears the mask bits of all four channels, enabling them to accept DMA requests.
I/O port 00Eh is used for channels 0–3 and I/O port 0DCh is used for channels 4–7.
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Clear Byte Pointer Flip-Flop
Master Clear
Clear Mask Register
Intel
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82801EB ICH5 / 82801ER ICH5R Datasheet