FW82801EB Intel, FW82801EB Datasheet - Page 114

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.6.2
114
All PCI DMA expansion agents must use the channel passing protocol described above. They must
also work as follows:
The three cases above require the following functionality in the PCI DMA expansion device:
PCI DMA Expansion Cycles
ICH5’s support of the PC/PCI DMA Protocol currently consists of four types of cycles: Memory-
to-I/O, I/O-to-Memory, Verify, and ISA Master cycles. ISA Masters are supported through the use
of a DMA channel that has been programmed for cascade mode.
The DMA controller does a two cycle transfer (a load followed by a store) as opposed to the ISA
"fly-by" cycle for PC/PCI DMA agents. The memory portion of the cycle generates a PCI memory
read or memory write bus cycle, its address representing the selected memory.
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If a PCI DMA expansion agent has more than one request active, it must resend the request
serial protocol after one of the requests has been granted the bus and it has completed its
transfer. The expansion device should drive its REQ# inactive for two clocks and then transmit
the serial channel passing protocol again, even if there are no new requests from the PCI
expansion agent to ICH5. For example: If a PCI expansion agent had active requests for DMA
channel 1 and channel 5, it would pass this information to ICH5 through the expansion
channel passing protocol. If after receiving GNT# (assume for CH5) and having the device
finish its transfer (device stops driving request to PCI expansion agent) it would then need to
re-transmit the expansion channel passing protocol to inform ICH5 that DMA channel 1 was
still requesting the bus, even if that was the only request the expansion device had pending.
If a PCI DMA expansion agent has a request go inactive before ICH5 asserts GNT#, it must
resend the expansion channel passing protocol to update ICH5 with this new request
information. For example: If a PCI expansion agent has DMA channel 1 and 2 requests
pending it sends them serially to ICH5 using the expansion channel passing protocol. If,
however, DMA channel 1 goes inactive into the expansion agent before the expansion agent
receives a GNT# from ICH5, the expansion agent MUST pull its REQ# line high for one clock
and resend the expansion channel passing information with only DMA channel 2 active. Note
that ICH5 does not do anything special to catch this case because a DREQ going inactive
before a DACK# is received is not allowed in the ISA DMA protocol and, therefore, does not
need to work properly in this protocol either. This requirement is needed to be able to support
Plug-n-Play ISA devices that toggle DREQ# lines to determine if those lines are free in the
system.
If a PCI expansion agent has sent its serial request information and receives a new DMA
request before receiving GNT# the agent must resend the serial request with the new request
active. For example: If a PCI expansion agent has already passed requests for DMA channel 1
and 2 and sees DREQ 3 active before a GNT is received, the device must pull its REQ# line
high for one clock and resend the expansion channel passing information with all three
channels active.
Drive REQ# inactive for one clock to signal new request information.
Drive REQ# inactive for two clocks to signal that a request that had been granted the bus has
gone inactive.
The REQ# and GNT# state machines must run independently and concurrently (i.e., a GNT#
could be received while in the middle of sending a serial REQ# or a GNT# could be active
while REQ# is inactive).
Intel
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82801EB ICH5 / 82801ER ICH5R Datasheet