FW82801EB Intel, FW82801EB Datasheet - Page 124

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.8.1
5.8.1.1
5.8.1.2
124
Table 46. Interrupt Status Registers
Table 47. Content of Interrupt Vector Byte
Acknowledging Interrupts
Interrupt Handling
Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt
level. These bits are used to determine the interrupt vector returned, and status of any other pending
interrupts.
The processor generates an interrupt acknowledge cycle that is translated by the host bridge into a
PCI Interrupt Acknowledge Cycle to the ICH5. The PIC translates this command into two internal
INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the
state of the interrupts for priority resolution. On the second INTA# pulse, the master or slave sends
the interrupt vector to the processor with the acknowledged interrupt code. This code is based upon
bits [7:3] of the corresponding ICW2 register, combined with three bits representing the interrupt
within that controller.
IMR
IRR
ISR
Bit
Master, Slave Interrupt
Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge
mode, and by an active high level in level mode. This bit is set whether or not the interrupt is
masked. However, a masked interrupt will not generate INTR.
Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt
acknowledge cycle is seen, and the vector returned is for that interrupt.
Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will
not generate INTR.
IRQ7,15
IRQ6,14
IRQ5,13
IRQ4,12
IRQ3,11
IRQ2,10
IRQ1,9
IRQ0,8
Table 46
defines the IRR, ISR, and IMR.
ICW2[7:3]
Bits [7:3]
Description
Intel
®
Bits [2:0]
82801EB ICH5 / 82801ER ICH5R Datasheet
110
101
100
011
010
001
000
111