FW82801EB Intel, FW82801EB Datasheet - Page 125

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.8.1.3
5.8.2
5.8.2.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Hardware/Software Interrupt Sequence
Initialization Command Words (ICWx)
Before operation can begin, each 8259 must be initialized. In the ICH5, this is a four byte
sequence. The four initialization command words are referred to by their acronyms: ICW1, ICW2,
ICW3, and ICW4.
The base address for each 8259 initialization command word is a fixed location in the I/O memory
space: 20h for the master controller, and A0h for the slave controller.
ICW1
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted
as a write to ICW1. Upon sensing this write, the ICH5 PIC expects three more byte writes to 21h
for the master controller, or A1h for the slave controller, to complete the ICW sequence.
A write to ICW1 starts the initialization sequence during which the following automatically occur:
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in
2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.
3. The processor acknowledges the INTR and responds with an interrupt acknowledge cycle. The
4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH5 converts it into the two
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set
6. Upon receiving the second internally generated INTA# pulse, the PIC returns the interrupt
7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of the second
1. Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to
2. The Interrupt Mask Register is cleared.
3. IRQ7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special mask mode is cleared and Status Read is set to IRR.
level mode, setting the corresponding IRR bit.
cycle is translated into a PCI interrupt acknowledge cycle by the host bridge. This command is
broadcast over PCI by the ICH5.
cycles that the internal 8259 pair can respond to. Each cycle appears as an interrupt
acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers.
and the corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave
identification code is broadcast by the master to the slave on a private, internal three bit wide
bus. The slave controller uses these bits to determine if it must respond with an interrupt vector
during the second INTA# pulse.
vector. If no interrupt request is present because the request was too short in duration, the PIC
returns vector 7 from the master controller.
INTA# pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued
at the end of the interrupt subroutine.
generate an interrupt.
Functional Description
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