FW82801EB Intel, FW82801EB Datasheet - Page 132

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.9.3.1
132
The following sequence is used:
Because they are edge triggered, the interrupts that are allocated to the PCI bus for this scheme may
not be shared with any other interrupt (such as the standard PCI PIRQ[A:D], those received via
SERIRQ#, or the internal level-triggered interrupts such as SCI or TCO).
The ICH5 ignores interrupt messages sent by PCI masters that attempt to use IRQ0, 2, 8, or 13.
Registers and Bits Associated with PCI Interrupt Delivery
Capabilities Indication
The capability to support PCI interrupt delivery are indicated via ACPI configuration techniques.
This involves the BIOS creating a data structure that gets reported to the ACPI configuration
software. The OS reads the PRQ bit in the APIC Version Register to see if the ICH5 is capable of
support PCI-based interrupt messages. As a precaution, the PRQ bit is not set if the XAPIC_EN bit
is not set.
Interrupt Message Register
The PCI devices all write their message into the IRQ Pin Assertion Register, which is a memory-
Mapped register located at the APIC base memory location + 20h.
1. During PCI PnP, the PCI peripheral is first programmed with an address
2. To cause the interrupt, the PCI peripheral requests the PCI bus and when granted, writes the
3. If the PRQ bit in the APIC Version Register is set, the ICH5 positively decodes the cycles (as a
4. The ICH5 decodes the binary value written to MESSAGE_ADDRESS and sets the appropriate
5. After sending the interrupt message to the processor, the ICH5 automatically clears the
(MESSAGE_ADDRESS) and data value (MESSAGE_DATA) that will be used for the
interrupt message delivery. For the ICH5, the MESSAGE_ADDRESS is the IRQ Pin
Assertion Register, which is mapped to memory location: FEC0_0020h.
MESSAGE_DATA value to the location indicated by the MESSAGE_ADDRESS. The
MESSAGE_DATA value indicates which interrupt occurred. This MESSAGE_DATA value is
a binary encoded. For example, to indicate that interrupt 7 should go active, the peripheral will
write a binary value of 0000111. The MESSAGE_DATA is a 32-bit value, although only the
lower 5 bits are used.
slave) in Medium time.
IRR bit in the internal I/O APIC. The corresponding interrupt must be set up for
edge-triggered interrupts. The ICH5 supports interrupts 00h through 23h. Binary values
outside this range do not cause any action.
interrupt.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet