FW82801EB Intel, FW82801EB Datasheet - Page 133

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.9.4
5.9.4.1
5.9.4.2
5.9.4.3
5.9.4.4
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: FSB Interrupt Delivery compatibility with processor clock control depends on the processor, not
Edge-Triggered Operation
Interrupt Message Format
Front Side Bus Interrupt Delivery
For processors that support Front Side Bus (FSB) interrupt delivery, the ICH5 requires that the I/O
APIC deliver interrupt messages to the processor in a parallel manner, rather than using the I/O
APIC serial scheme.
This is done by the ICH5 writing (via the hub interface) to a memory location that is snooped by
the processor(s). The processor(s) snoop the cycle to know which interrupt goes active.
The following sequence is used:
the ICH5.
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt.
Level-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt.
If after the EOI the interrupt is still active, then another “Assert Message” is sent to indicate that the
interrupt is still active.
Registers Associated with Front Side Bus Interrupt Delivery
Capabilities Indication: The capability to support Front Side Bus interrupt delivery is indicated
via ACPI configuration techniques. This involves the BIOS creating a data structure that gets
reported to the ACPI configuration software.
The ICH5 writes the message to PCI (and to the Host controller) as a 32-bit memory write cycle. It
uses the formats shown in
The local APIC (in the processor) has a delivery mode option to interpret Front Side Bus messages
as a SMI in which case the processor treats the incoming interrupt as a SMI instead of as an
interrupt. This does not mean that the ICH5 has any way to have a SMI source from ICH5 power
management logic cause the I/O APIC to send an SMI message (there is no way to do this). The
ICH5’s I/O APIC can only send interrupts due to interrupts which do not include SMI, NMI or
INIT. This means that in IA32/IA64 based platforms, Front Side Bus interrupt message format
delivery modes 010 (SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, must not
be used and is not supported. Only the hardware pin connection is supported by ICH5.
1. When the ICH5 detects an interrupt event (active edge for edge-triggered mode or a change for
2. Internally, the ICH5 requests to use the bus in a way that automatically flushes upstream
3. The ICH5 then delivers the message by performing a write cycle to the appropriate address
level-triggered mode), it sets or resets the internal IRR bit associated with that interrupt.
buffers. This can be internally implemented similar to a DMA device request.
with the appropriate data. The address and data formats are described below in
Table 49
and
Table 50
for the address and data.
Functional Description
Section
5.9.4.4.
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