FW82801EB Intel, FW82801EB Datasheet - Page 138

no-image

FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FW82801EB
Manufacturer:
INTEL
Quantity:
20 000
Part Number:
FW82801EB SL73Z
Manufacturer:
INTEL
Quantity:
238
Part Number:
FW82801EB(SL73Z)
Manufacturer:
INTEL
Quantity:
20 000
Functional Description
5.11.1
5.11.2
138
Warning:
Note: The leap year determination for adding a 29th day to February does not take into account the
The time and calendar data should match the data mode (BCD or binary) and hour mode
(12 or 24 hour) as selected in register B. It is up to the programmer to make sure that data stored in
these locations is within the reasonable values ranges and represents a possible date and time. The
exception to these ranges is to store a value of C0–FF in the Alarm bytes to indicate a don’t care
situation. All Alarm conditions must match to trigger an Alarm Flag, which could trigger an Alarm
Interrupt if enabled. The SET bit must be 1 while programming these locations to avoid clashes
with an update cycle. Access to time and date information is done through the RAM locations. If a
RAM read from the ten time and date bytes is attempted during an update cycle, the value read do
not necessarily represent the true contents of those locations. Any RAM writes under the same
conditions are ignored.
end-of-the-century exceptions. The logic simply assumes that all years divisible by 4 are leap
years. According to the Royal Observatory Greenwich, years that are divisible by 100 are typically
not leap years. In every fourth century (years divisible by 400, like 2000), the 100-year-exception
is over-ridden and a leap-year occurs. Note that the year 2100 will be the first time in which the
current RTC implementation would incorrectly calculate the leap-year.
The ICH5 does not implement month/year alarms.
Update Cycles
An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide
chain is properly configured. During this procedure, the stored time and date are incremented,
overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to
the RAM locations. The update cycle will start at least 488 µs after the UIP bit of register A is
asserted, and the entire cycle does not take more than 1984 µs to complete. The time and date RAM
locations (0
To avoid update and data corruption conditions, external RAM access to these locations can safely
occur at two times. When a updated-ended interrupt is detected, almost 999 ms is available to read
and write the valid time and date data. If the UIP bit of Register A is detected to be low, there is at
least 488 µs before the update cycle begins.
The overflow conditions for leap years and daylight savings adjustments are based on more than
one date or time item. To ensure proper operation when adjusting the time, the new time and data
values should be set at least two seconds before one of these conditions (leap year, daylight savings
time adjustments) occurs.
Interrupts
The real-time clock interrupt is internally routed within the ICH5 both to the I/O APIC and the
8259. It is mapped to interrupt vector 8. This interrupt does not leave the ICH5, nor is it shared with
any other interrupt. IRQ8# from the SERIRQ stream is ignored.
9) are disconnected from the external bus during this time.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet

Related parts for FW82801EB