FW82801EB Intel, FW82801EB Datasheet - Page 148

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

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Functional Description
5.13.3
s
5.13.4
5.13.5
148
Table 61. System Power Plane
System Power Planes
The system has several independent power planes, as described in
particular power plane is shut off, it should go to a 0 V level.
Intel
The ICH5 power planes are previously defined in
within the ICH5, there are many interface signals that go to devices that may be powered down.
These include:
SMI#/SCI Generation
On any SMI# event taking place, ICH5 asserts SMI# to the processor, which causes it to enter
SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is set, SMI# goes
inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI# is driven active again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In
non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts (IRQ
9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that interrupt.
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The
interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not;
(see Section 9.1.11 ACPI Control Register for
sources are removed.
DEVICE[n]
MEMORY
Plane
IDE:
USB:
AC ’97:
MAIN
CPU
®
ICH5 Power Planes
ICH5 can tri-state or drive low all IDE output signals and shut off input buffers.
ICH5 can tri-state USB output signals and shut off input buffers if USB wakeup is
not desired
ICH5 can drive low the outputs and shut off inputs
Controlled
SLP_S3#
SLP_S3#
SLP_S4#
signal
signal
signal
GPIO
By
The SLP_S3# signal can be used to cut the power to the processor
completely.
When SLP_S3# goes active, power can be shut off to any circuit not
required to wake the system from the S3 state. Since the S3 state requires
that the memory context be preserved, power must be retained to the main
memory.
The processor, devices on the PCI bus, LPC I/F downstream hub interface
and AGP will typically be shut off when the Main power plane is shut,
although there may be small subsections powered.
When the SLP_S4# goes active, power can be shut off to any circuit not
required to wake the system from the S4. Since the memory context does
not need to be preserved in the S4 state, the power to the memory can also
be shut down.
Individual subsystems may have their own power plane. For example, GPIO
signals may be used to control the power to disk drives, audio amplifiers, or
the display screen.
details.) The interrupt remains asserted until all SCI
Intel
Section
®
82801EB ICH5 / 82801ER ICH5R Datasheet
3.1. Although not specific power planes
Description
Table
61. Note that when a

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