FW82801EB Intel, FW82801EB Datasheet - Page 150

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

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Functional Description
5.13.6
150
Table 62. Causes of SMI# and SCI (Sheet 2 of 2)
NOTES:
Dynamic Processor Clock Control
The ICH5 has extensive control for dynamically starting and stopping system clocks. The clock
control is used for transitions among the various S0/Cx states, and processor throttling. Each
dynamic clock control method is described in this section. The various sleep states may also
perform types of non-dynamic clock control.
The ICH5 supports the ACPI C0 and C1 states.
The Dynamic Processor Clock control is handled using the following signals:
The C1 state is entered based on the processor performing an auto halt instruction.
A C1 state ends due to a Break event. Based on the break event, the ICH5 returns the system to C0
state.
1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3. GBL_SMI_EN must be 1 to enable SMI.
4. EOS must be written to 1 to re-enable SMI for the next 1.
Enhanced USB Legacy Support
Event
Enhanced USB Intel Specific
Event
UHCI USB Legacy logic
Serial IRQ SMI reported
Device monitors match address in
its range
SMBus Host Controller
SMBus Slave SMI message
SMBus SMBALERT# signal active
SMBus Host Notify message
received
Access microcontroller 62h/66h
SLP_EN bit written to 1
STPCLK#:
Cause
SCI
No
No
No
No
No
No
No
No
No
No
No
Used to halt processor instruction stream.
SMI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Intel
HOST_NOTIFY_INTREN
LEGACY_USB2_EN = 1
Host Controller Enabled
LEGACY_USB_EN=1
INTEL_USB2_EN = 1
DEV[n]_TRAP_EN=1
SMI_ON_SLP_EN=1
Additional Enables
®
82801EB ICH5 / 82801ER ICH5R Datasheet
SMB_SMI_EN
MCSMI_EN
none
none
none
SMI_ON_SLP_EN_STS
SMBus host status reg.
LEGACY_USB2_STS
HOST_NOTIFY_STS
LEGACY_USB_STS
DEV[n]_TRAP_STS
SERIRQ_SMI_STS
INTEL_USB2_STS
SMBUS_SMI_STS
SMBUS_SMI_STS
SMBUS_SMI_STS
Where Reported
DEVMON_STS,
MCSMI_STS

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