FW82801EB Intel, FW82801EB Datasheet - Page 152

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.13.7.2
5.13.7.3
152
Table 63. Sleep Types
Initiating Sleep State
Sleep states (S1–S5) are initiated by:
Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the system to a full
on state (S0), although some non-critical subsystems might still be shut off and have to be brought
back manually. For example, the hard disk may be shut off during a sleep state, and have to be
enabled via a GPIO pin before it can be used.
Upon exit from the ICH5-controlled Sleep states, the WAK_STS bit is set. The possible causes of
Wake Events (and their restrictions) are shown in
Sleep Type
•
•
Masking interrupts, turning off all bus master enable bits, setting the desired type in the
SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts to gracefully
put the system into the corresponding Sleep state.
Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override
event. In this case the transition to the S5 state is less graceful, since there are no dependencies
on observing Stop-Grant cycles from the processor or on clocks other than the RTC clock.
S1
S3
S4
S5
Intel
lowers the processor’s power consumption. No snooping is possible in this state.
ICH5 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is
only retained to devices needed to wake from this sleeping state, as well as to the memory.
ICH5 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to the memory
subsystem. Only devices needed to wake from this state should be powered.
Same power state as S4. ICH5 asserts SLP_S3#, SLP_S4# and SLP_S5#.
®
ICH5 asserts the STPCLK# signal. It also has the option to assert CPUSLP# signal. This
Intel
Table
Comment
®
82801EB ICH5 / 82801ER ICH5R Datasheet
64.