FW82801EB Intel, FW82801EB Datasheet - Page 165

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.14.1
5.14.1.1
5.14.1.2
5.14.1.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: The INTRD_DET bit resides in the ICH5’s RTC well, and is set and cleared synchronously with
Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the
Handling an Intruder
Detecting Improper Flash BIOS Programming
Theory of Operation
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management functionality be
provided without the aid of an external microcontroller.
Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch
the first instruction after reset, the TCO timer times out twice and the ICH5 asserts PCIRST#.
The ICH5 has an input signal, INTRUDER#, that can be attached to a switch that is activated by
the system’s case being open. This input has a two RTC clock debounce. If INTRUDER# goes
active (after the debouncer), this will set the INTRD_DET bit in the TCO_STS register. The
INTRD_SEL bits in the TCO_CNT register can enable the ICH5 to cause an SMI# or interrupt.
The BIOS or interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN
bit.
The software can also directly read the status of the INTRUDER# signal (high or low) by clearing
and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder
function is not required.
If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1,
then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note
that this is slightly different than a classic sticky bit, since most sticky bits would remain active
indefinitely when the signal goes active and would immediately go inactive when a 1 is written to
the bit.
the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1 to the bit
location) there may be as much as two RTC clocks (about 65 µs) delay before the bit is actually
cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms to guarantee that
the INTRD_DET bit will be set.
bit remains set and the SMI is generated again immediately. The SMI handler can clear the
INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal goes inactive and
then active again, there will not be further SMIs, since the INTRD_SEL bits would select that no
SMI# be generated.
The ICH5 can detect the case where the flash BIOS is not programmed. This results in the first
instruction fetched to have a value of FFh. If this occurs, the ICH5 sets the BAD_BIOS bit, which
can then be reported via the Heartbeat and Event reporting using an external, Alert on LAN
enabled LAN controller (See
Section
5.14.2).
Functional Description
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