FW82801EB Intel, FW82801EB Datasheet - Page 166

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.14.1.4
5.14.2
166
Handling an ECC Error or Other Memory Error
The Host controller provides a message to indicate that it would like to cause an SMI#, SCI,
SERR#, or NMI. The software must check the host controller as to the exact cause of the error.
Heartbeat and Event Reporting via SMBUS
The ICH5 integrated LAN controller supports ASF heartbeat and event reporting functionality
when used with the 82562EM or 82562EZ Platform LAN Connect component. This allows the
integrated LAN controller to report messages to a network management console without the aid of
the system processor. This is crucial in cases where the processor is malfunctioning or cannot
function due to being in a low-power state.
All heartbeat and event messages are sent on the SMBus interface. This allows an external LAN
controller to act upon these messages if the internal LAN controller is not used.
The basic scheme is for the ICH5 integrated LAN controller to send a prepared Ethernet message
to a network management console. The prepared message is stored in the non-volatile EEPROM
that is connected to the ICH5.
Messages are sent by the LAN controller either because a specific event has occurred, or they are
sent periodically (also known as a heartbeat). The event and heartbeat messages have the exact
same format. The event messages are sent based on events occurring. The heartbeat messages are
sent every 30 to 32 seconds. When an event occurs, the ICH5 sends a new message and increments
the SEQ[3:0] field. For heartbeat messages, the sequence number does not increment.
The following rules/steps apply if the system is in a G0 state and the policy is for the ICH5 to
reboot the system after a hardware lockup:
1. On detecting the lockup, the SECOND_TO_STS bit is set. The ICH5 may send up to 1 Event
2. If the reboot at step 1 is successful then the BIOS should clear the SECOND_TO_STS bit.
3. If the reboot attempt in step 1 is not successful, the timer will timeout a third time. At this point
4. After step 3 (unsuccessful reboot after third timeout), if the user does a Power Button
5. After step 4 (power button override after unsuccessful reboot) if the user presses the Power
6. If step 5 (power button press) is successful in waking the system, the ICH5 continues sending
message to the LAN controller. The ICH5 then attempts to reboot the processor.
This prevents any further Heartbeats from being sent. The BIOS may then perform addition
recovery/boot steps. (See note 2, below.)
the system has locked up and was unsuccessful in rebooting. The ICH5 does not attempt to
automatically reboot again. The ICH5 starts sending a message every heartbeat period
(30–32 seconds). The heartbeats continue until some external intervention occurs (reset, power
failure, etc.).
Override, the system goes to an S5 state. The ICH5 continues sending the messages every
heartbeat period.
Button again, the system should wake to an S0 state and the processor should start executing
the BIOS.
messages every heartbeat period until the BIOS clears the SECOND_TO_STS bit. (See note 2)
Intel
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82801EB ICH5 / 82801ER ICH5R Datasheet