FW82801EB Intel, FW82801EB Datasheet - Page 172

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
172
Table 74. GPIO Implementation (Sheet 3 of 4)
GPIO[28:27]
GPIO[31:29]
GPIO[39:35]
GPIO25
GPIO26
GPIO32
GPIO33
GPIO34
GPIO40
GPIO41
GPIO24
GPIO
Type
Input
Input
Only
Only
N/A
N/A
N/A
N/A
I/O
I/O
I/O
I/O
I/O
Alternate
Function
Unmuxed
Unmuxed
Unmuxed
Unmuxed
LDRQ1#
(Note 1)
REQ4#
N/A
N/A
N/A
N/A
N/A
Resume
Resume
Resume
Power
Core
Core
Core
Core
Well
N/A
N/A
N/A
N/A
Tolerant
Intel
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
®
82801EB ICH5 / 82801ER ICH5R Datasheet
• Input active status read from GP_LVL
• Output controlled via GP_LVL register
• TTL driver output
• Blink enabled via GPO_BLINK register
• Input active status read from GP_LVL
• Output controlled via GP_LVL register
• TTL driver output
• Not implemented
• Blink enabled via GPO_BLINK register
• Input active status read from GP_LVL
• Output controlled via GP_LVL register
• TTL driver output
• Not implemented
• Input active status read from GP_LVL
• Output controlled via GP_LVL2 register
• TTL driver output
• Not implemented
• Input active status read from GP_LVL
• Output controlled via GP_LVL2 register
• TTL driver output
• Not implemented
• GPIO_USE_SEL bit 40 enables REQ/
• Input active status read from GP_LVL2
• TTL driver output
• GPIO_USE_SEL bit 41 enables LDRQ1#.
• TTL driver output
register bit 24.
bit 24.
(D31:F0: Offset GPIOBASE+18h) bit 25
register bit 25
bit 25.
(D31:F0: Offset GPIOBASE+18h) bits
[28:27]
register bits [27:28]
bits [27:28]
register bit 32
bit 32
register bit 34
bit 34
GNT4# pair.
register bit 40
Input active status read from GP_LVL2
register bit 41
Notes