FW82801EB Intel, FW82801EB Datasheet - Page 173

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.15.2
5.15.3
Intel
®
Table 74. GPIO Implementation (Sheet 4 of 4)
82801EB ICH5 / 82801ER ICH5R Datasheet
SMI# and SCI Routing
NOTES:
Power Wells
Some GPIOs exist in the resume power plane. Care must be taken to make sure GPIO signals are
not driven high into powered-down planes.
Some ICH5 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs
are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override
event results in the ICH5 driving a pin to a logic 1 to another device that is powered down.
GPIO[1:15] have “sticky” bits on the input. Refer to the GPE0_STS register. As long as the signal
goes active for at least 2 clocks, the ICH5 keeps the sticky status bit active. The active level can be
selected in the GP_LVL register.
If the system is in an S0 or an S1 state, the GPI inputs are sampled at 33 MHz, so the signal only
needs to be active for about 60 ns to be latched. In the S3–S5 states, the GPI inputs are sampled at
32.768 kHz, and thus must be active for at least 61 microseconds to be latched.
If the input signal is still active when the latch is cleared, it will again be set. Another edge trigger
is not required. This makes these signals “level” triggered inputs.
The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither. Note that a
bit can be routed to either an SMI# or an SCI, but not both.
1. All GPIOs default to their alternate function.
2. All inputs are sticky. The status bit remains set as long as the input was asserted for two clocks. GPIs are
3. GPIO[0:7] are 5 V tolerant, and all GPIs can be routed to cause an SCI or SMI#.
4. If GPIO_USE_SEL bit 1 is set to 1 and GEN_CNT bit 25 is also set to 1 then REQ/GNT5# is enabled. See
GPIO[47:42]
GPIO48
GPIO49
sampled on PCI clocks in S0/S1. GPIs are sampled on RTC clocks in S3/S4/S5.
Section
GPIO
9.1.22.
Output
Output
Type
Only
Only
N/A
CPUPWRGD
Alternate
Function
(Note 1)
GNT4#
N/A
CPU I/F
Power
Core
Well
N/A
Tolerant
3.3 V
3.3 V
• Not implemented
• Output controlled via GP_LVL2 register
• TTL driver output
• GPIO_USE_SEL bit 49 enables
• Output controlled via GP_LVL2 register
• TTL driver output
bit 48
CPUPWRGD.
bit 49
Functional Description
Notes
173