FW82801EB Intel, FW82801EB Datasheet - Page 174

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.16
5.16.1
5.16.1.1
174
Note: The primary and secondary channels are controlled by separate bits, allowing one to be in native
IDE Port Decode
IDE Controller (D31:F1)
The ICH5 IDE controller features two sets of interface signals (Primary and Secondary) that can be
independently enabled, tri-stated or driven low. In addition, the ICH5 IDE controller supports both
legacy mode and native mode IDE interface. In native mode, the IDE controller is a fully PCI
compliant software interface and does not use any legacy I/O or interrupt resources.
The IDE interfaces of the ICH5 can support several types of data transfers:
PIO Transfers
The ICH5 IDE controller includes both compatible and fast timing modes. The fast timing modes
can be enabled only for the IDE data ports. All other transactions to the IDE registers are run in
single transaction mode with compatible timings.
Up to two IDE devices may be attached per IDE connector (drive 0 and drive 1). The IDETIM and
SIDETIM Registers permit different timing modes to be programmed for drive 0 and drive 1 of the
same connector.
The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each drive by
programming the IDE I/O Configuration register and the Synchronous DMA Control and Timing
registers. When a drive is enabled for synchronous DMA mode operation, the DMA transfers are
executed with the synchronous DMA timings. The PIO transfers are executed using compatible
timings or fast timings if also enabled.
The Command and Control Block registers are accessed differently depending on the decode
mode, which is selected by the Programming Interface configuration register (Offset 09h).
mode and the other in legacy mode simultaneously.
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Programmed I/O (PIO): Processor is in control of the data transfer.
8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it does not
use the 8237 in the ICH5. This protocol off loads the processor from moving data. This allows
higher transfer rate of up to 16 MB/s.
Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both host and
target throttling of data and transfer rates of up to 33 MB/s.
Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both host and
target throttling of data and transfer rates of up to 66 MB/s.
Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both host and
target throttling of data and transfer rates of up to 100 MB/s.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet