FW82801EB Intel, FW82801EB Datasheet - Page 179

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.16.2.5
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Native Mode
In this case both the Primary and Secondary channels share an interrupt. It is internally connected
to PIRQC# (IRQ18 in APIC mode). The interrupt is active-low and shared.
Behavioral notes in native mode
Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following steps are
required:
The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers
terminate when the physical region described by the last PRD in the table has been completely
transferred. The active bit in the Status Register is reset and the DDRQ signal is masked.
1. Software prepares a PRD table in system memory. The PRD table must be DWord aligned and
2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a 1 to the Start bit in the Command
5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.
6. The controller transfers data to/from memory responding to DMA requests from the IDE
7. At the end of the transfer, the IDE device signals an interrupt.
8. In response to the interrupt, software resets the Start/Stop bit in the command register. It then
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The IRQ14 and IRQ15 pins do not affect the internal IRQ14 and IRQ15 inputs to the interrupt
controllers. The IDE logic forces these signals inactive in such a way that the Serial IRQ
source may be used.
The IRQ14 and IRQ15 inputs (not external IRQ[14:15] pins) to the interrupt controller can
come from other sources (Serial IRQ, PIRQx).
The IRQ14 and IRQ15 pins are inverted from active-high to the active-low PIRQ.
When switching the IDE controller to native mode, the IDE Interrupt Pin Register
(see
interrupt is still active when the masking ends, the interrupt is allowed to be asserted.
must not cross a 64-KB boundary.
Register. The direction of the data transfer is specified by setting the Read/Write Control bit.
The interrupt bit and Error bit in the Status register are cleared.
Register. The first entry in the PRD table is fetched and loaded into two registers which are not
visible by software, the Current Base and Current Count registers. These registers hold the
current value of the address and byte count loaded from the PRD table. The value in these
registers is only valid when there is an active command to an IDE device.
device. The IDE device and the host controller may or may not throttle the transfer several
times. When the last data transfer for a region has been completed on the IDE interface, the
next descriptor is fetched from the table. The descriptor contents are loaded into the Current
Base and Current Count registers.
reads the controller status followed by the drive status to determine if the transfer completed
successfully.
Section
10.1.18) is masked. If an interrupt occurs while the masking is in place and the
Functional Description
179