FW82801EB Intel, FW82801EB Datasheet - Page 183

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.16.4
5.16.5
5.16.6
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle Time (CT)
Ultra ATA/100 Protocol
Ultra ATA/33/66/100 Timing
Ultra ATA/66 Protocol
In addition to Ultra ATA/33, the ICH5 supports the Ultra ATA/66 protocol. The Ultra ATA/66
protocol is enabled via configuration bits 3:0 at offset 54h. The two protocols are similar, and are
intended to be device driver compatible. The Ultra ATA/66 logic can achieve transfer rates of up to
66 MB/s.
To achieve the higher data rate, the timings are shortened and the quality of the cable is improved
to reduce reflections, noise, and inductive coupling. Note that the improved cable is required and
still plugs into the standard IDE connector.
The Ultra ATA/66 protocol also supports a 44 MB/s mode.
When the ATA_FAST bit is set for any of the four IDE devices, then the timings for the transfers to
and from the corresponding device run at a higher rate. The ICH5 Ultra ATA/100 logic can achieve
read transfer rates up to 100 MB/s, and write transfer rates up to 88.9 MB/s.
The cable improvements required for Ultra ATA/66 are sufficient for Ultra ATA/100, so no further
cable improvements are required when implementing Ultra ATA/100.
The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing
register and the IDE Configuration register. Different timings can be programmed for each drive in
the system. The Base Clock frequency for each drive is selected in the IDE Configuration register.
The Cycle Time (CT) and Ready to Pause (RP) time (defined as multiples of the Base Clock) are
programmed in the Synchronous DMA Timing Register. The Cycle Time represents the minimum
pulse width of the data strobe (STROBE) signal. The Ready to Pause time represents the number of
Base Clock periods that the ICH5 waits from deassertion of DMARDY# to the assertion of STOP
when it desires to stop a burst read transaction.
must be set for three Base Clocks. The ICH5 thus toggles the write strobe signal every 22.5 ns,
transferring two bytes of data on each strobe edge. This means that the ICH5 performs Mode 5
write transfers at a maximum rate of 88.9 MB/s. For read transfers, the read strobe is driven by the
ATA/100 device, and the ICH5 supports reads at the maximum rate of 100 MB/s.
Functional Description
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