FW82801EB Intel, FW82801EB Datasheet - Page 184

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.16.7
5.16.8
184
Warning:
IDE Swap Bay
To support a swap bay, the ICH5 allows the IDE output signals to be tri-stated and input buffers to
be turned off. This should be done prior to the removal of the drive. The output signals can also be
driven low. This can be used to remove charge built up on the signals. Configuration bits are
included in the IDE I/O Configuration register, offset 54h in the IDE PCI configuration space.
In an IDE Hot Swap Operation, an IDE device is removed and a new one inserted while the IDE
interface is powered down and the rest of the system is in a fully powered-on state (SO). During an
IDE Hot Swap, if the operating system executes cycles to the IDE interface after it has been
powered down it will cause the ICH5 to hang the system that is waiting for IORDY to be asserted
from the drive.
To correct this issue, the following BIOS procedures are required for performing an IDE hot swap:
Software should not attempt to control the outputs (either tri-state or driving low), while an IDE
transfer is in progress. Unpredictable results could occur, including a system lockup.
SMI Trapping (APM)
Offset 48h, bits 3:0 in the power management I/O space (see
generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges
(1F0
addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be
forwarded to the IDE controller, and for an SMI# to be generated. If an access to the Bus-Master
IDE registers occurs while trapping is enabled for the device being accessed, then the register is
updated, an SMI# is generated, and the device activity status bits
indicating that a trap occurred. To block accesses to the native IDE ranges, software must use the
generic power management control registers described in
1. Program IDE SIG_MODE (Configuration register at offset 54h) to 10b (drive low mode).
2. Clear IORDY Sample Point Enable (bits 1 or 5 of IDE Timing reg.). This prevents the ICH5
from waiting for IORDY assertion when the operating system accesses the IDE device after
the IDE drive powers down, and ensures that 0s are always be returned for read cycles that
occur during hot swap operation.
–
1F7h, 3F6h, 170
–
177h, and 376h). If the IDE controller is in legacy mode and is using these
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Section
Section
(Section
9.8.1.
9.10.14) contain control for
9.10.13) are updated