FW82801EB Intel, FW82801EB Datasheet - Page 189

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

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5.18.1
5.18.2
5.18.3
Intel
®
Table 80. Legacy Routing
82801EB ICH5 / 82801ER ICH5R Datasheet
The registers associated with these timers are mapped to a memory space (much like the I/O
APIC). However, it is not implemented as a standard PCI function. The BIOS reports to the
operating system the location of the register space. The hardware can support an assignable decode
space; however, the BIOS sets this space prior to handing it over to the operating system
(See
once it is set by the BIOS.
Timer Accuracy
The main counter is clocked by the 14.31818 MHz clock, synchronized into the 66.666 MHz
domain. This results in a non-uniform duty cycle on the synchronized clock, but does have the
correct average period. The accuracy of the main counter is as accurate as the 14.3818 MHz clock.
Interrupt Mapping
Mapping Option #1 (Legacy Option)
In this case, the Legacy Rout bit (LEG_RT_CNF) is set. This forces the mapping found in
Table
Mapping Option #2 (Standard Option)
In this case, the Legacy Rout bit (LEG_RT_CNF) is 0. Each timer has its own routing control. The
supported interrupt values are IRQ 20, 21, 22, and 23.
Periodic vs. Non-Periodic Modes
Non-Periodic Mode
When a timer is set up for non-periodic mode, it generates a value in the main counter that matches
the value in the timer’s comparator register. If the timer is set up for 32-bit mode, then it generates
another interrupt when the main counter wraps around and matches this same value again. Timer 0
is configurable to 32 (default) or 64-bit mode, whereas Timers 1 and 2 only support 32-bit mode
(See
1. The timers are accurate over any 1 ms period to within 0.05% of the time specified in the timer
2. Within any 100 microsecond period, the timer reports a time that is up to two ticks too early or
3. The timer is monotonic. It does not return the same value on two consecutive reads (unless the
Timer
resolution fields.
too late. Each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%.
counter has rolled over and reached the same value).
Section
0
1
2
Section
80.
6.4). It is not expected that the operating system will move the location of these timers
17.5).
Per IRQ Routing Field.
8259 Mapping
IRQ0
IRQ8
Per IRQ Routing Field
APIC Mapping
IRQ2
IRQ8
In this case, the 8254 timer will not
cause any interrupts
In this case, the RTC will not cause any
interrupts.
Functional Description
Comment
189

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