FW82801EB Intel, FW82801EB Datasheet - Page 191

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.18.4
5.18.5
5.18.6
5.18.7
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Interrupt Levels
Handling Interrupts
Issues Related to 64-Bit Timers with 32-Bit Processors
Enabling the Timers
The BIOS or OS PnP code should route the interrupts. This includes the Legacy Rout bit, Interrupt
Rout bit (for each timer), interrupt type (to select the edge or level type for each timer)
The Device Driver code should do the following for an available timer:
Interrupts directed to the internal 8259s are active high.
the polarity programming of the I/O APIC for detecting internal interrupts.
If the interrupts are mapped to the I/O APIC and set for level-triggered mode, they can be shared
with PCI interrupts. This may be shared although it’s unlikely for the OS to attempt to do this.
If more than one timer is configured to share the same IRQ (using the TIMERn_INT_ROUT_CNF
fields), then the software must configure the timers to level-triggered mode. Edge-triggered
interrupts cannot be shared.
If each timer has a unique interrupt and the timer has been configured for edge-triggered mode,
then there are no specific steps required. No read is required to process the interrupt.
If a timer has been configured to level-triggered mode, then its interrupt must be cleared by the
software. This is done by reading the interrupt status register and writing a 1 back to the bit position
for the interrupt to be cleared.
Independent of the mode, software can read the value in the main counter to see how time has
passed between when the interrupt was generated and when it was first serviced.
If Timer 0 is set up to generate a periodic interrupt, the software can check to see how much time
remains until the next interrupt by checking the timer value register.
A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit instructions.
However, a 32-bit processor may not be able to directly read 64-bit timer. A race condition comes
up if a 32-bit processor reads the 64-bit register using two separate 32-bit reads. The danger is that
just after reading one half, the other half rolls over and changes the first half.
If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both
the upper and lower 32-bits of the timer. If a 32-bit processor does not want to halt the timer, it can
use the 64-bit timer as a 32-bit timer by setting the TIMERn_32MODE_CNF bit. This causes the
timer to behave as a 32-bit timer. The upper 32-bits are always 0.
1. Set the Overall Enable bit (Offset 04h, bit 0).
2. Set the timer type field (selects one-shot or periodic).
3. Set the interrupt enable
4. Set the comparator value
SeeSection 5.9
for information regarding
Functional Description
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