FW82801EB Intel, FW82801EB Datasheet - Page 195

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 83. TD Control and Status (Sheet 2 of 2)
82801EB ICH5 / 82801ER ICH5R Datasheet
15:11
10:0
17
Bit
22
21
20
19
18
16
Stalled.
1 = Set to a 1 by the ICH5 during status updates to indicate that a serious error has occurred at the
Data Buffer Error (DBE).
1 = Set to a 1 by the ICH5 during status update to indicate that the ICH5 is unable to keep up with
Babble Detected (BABD).
1 = Set to a 1 by the ICH5 during status update when “babble” is detected during the transaction
Negative Acknowledgment (NAK) Received (NAKR).
1 = Set to a 1 by the ICH5 during status update when the ICH5 receives a “NAK” packet during the
CRC/Time Out Error (CRC_TOUT).
1 = Set to a 1 by the ICH5 as follows:
In the transmit case (OUT or SETUP Command), this is in response to the ICH5 detecting a timeout
from the target device/endpoint.
In the receive case (IN Command), this is in response to the ICH5’s CRC checker circuitry detecting
an error on the data received from the device/endpoint or a NAK or STALL handshake being
received in response to a SETUP transaction.
Bit stuff Error (BSE).
1 = This bit is set to a 1 by the ICH5 during status update to indicate that the receive data stream
Bus Turn Around Time-out (BTTO).
1 = This bit is set to a 1 by the ICH5 during status updates to indicate that a bus time-out condition
Reserved
Actual Length (ACTLEN). The Actual Length field is written by the ICH5 at the conclusion of a USB
transaction to indicate the actual number of bytes that were transferred. It can be used by the
software to maintain data integrity. The value programmed in this register is encoded as n-1 (see
Maximum Length field description in the TD Token).
• During a status update in the case that no response is received from the target device/endpoint
• During a status update when a Cycli Redundancy Check (CRC) error is detected during the
within the time specified by the protocol chapter of the Universal Serial Bus Revision 2.0
Specification.
transaction associated with this transfer descriptor.
device/endpoint addressed by this TD. This can be caused by babble, the error counter
counting down to 0, or reception of the STALL handshake from the device during the
transaction. Any time that a transaction results in the Stalled bit being set, the Active bit is also
cleared (set to 0). If a STALL handshake is received from a SETUP transaction, a Time Out
Error will also be reported.
the reception of incoming data (overrun) or is unable to supply data fast enough during
transmission (underrun). When this occurs, the actual length and Max Length field of the TD
does not match. In the case of an underrun, the ICH5 transmits an incorrect CRC (thus,
invalidating the data at the endpoint) and leaves the TD active (unless error count reached 0). If
a overrun condition occurs, the ICH5 forces a timeout condition on the USB, invalidating the
transaction at the source.
generated by this descriptor. Babble is unexpected bus activity for more than a preset amount
of time. In addition to setting this bit, the ICH5 also sets the” STALLED” bit (bit 22) to a 1. Since
“babble” is considered a fatal error for that transfer, setting the” STALLED” bit to a 1 insures that
no more transactions occur as a result of this descriptor. Detection of babble causes immediate
termination of the current frame. No further TDs in the frame are executed. Execution resumes
with the next frame list index.
transaction generated by this descriptor. If a NAK handshake is received from a SETUP
transaction, a Time Out Error will also be reported.
contained a sequence of more than six 1s in a row.
was detected for this USB transaction. This time-out is specially defined as not detecting an
IDLE-to ‘K’ state Start of Packet (SOP) transition from 16 to 18 bit times after the SE0-to IDE
transition of previous End of Packet (EOP).
Description
Functional Description
195